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Qualcomm
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Physical Design Engineer, Senior

Physical Design Engineer, Senior

Qualcomm

2 - 7 years

13 - 17 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

perl tcl hardware engineering node pnr dsp physical design soc floorplan power analysis fpga drc linux synthesis sta cts primetime lvs timing analysis physical verification floor planning rf timing closure placement unix clock tree synthesis

Work Mode

Work from Office

Job Type

Full Time

Job Description

General Summary:

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
PNR implementation for Qualcomm SoC's
Good hands-on experience on Floorplanning, PNR and STA flows
Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc
Good understanding on signoff domains LEC/CLP/PDN knowledge, etc
Good knowledge on Unix/Linux Perl/TCL fundamentals/scripting

Principal Duties and responsibilities:

Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes.
Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)
Quick learner with good analytical and problem solving skills

Qualifications:

3+ years Hardware Engineering experience or related work experience.
2+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm)

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Physical Design Engineer, Senior