472 Physical Verification Jobs

Skills/Experience: Hands on debugging skills in different physical verification checks like LVS, DRC, ERC, PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. Working experience in cutting edge technologies such as 3/4/5nm and 7nm process nodes is desired Experience (years) : 4+ Year Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

About The Role About The Role : 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is necessary. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc. Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience and collaborating with cross functional teams will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Multiple foundries experience is an added plus. Minimum Educational Qualification : Educational Bachelor"s, Electrical or Electronics Engineering or equivalent Role And Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, EM, quality check and documentation. Responsible for on-time delivery of block-level/top-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Should have good experience in working with cross-functional team. Ensure standard processes and procedures are followed to resolve all client queries. Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations to timely deliverable with high quality. Troubleshoot all client queries in a user-friendly, courteous, and professional manner. Offer alternative solutions to clients (where appropriate) with the objective of retaining customers" and clients" business. Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client. Contribute to effective project-management. Effectively communicating with engineering teams in different Geographical locations to assure the success of the layout project. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders.

What will you do As lead of costing function for the AIS Operations at the factory in Kalwa - Arioli, Thane Maharashtra under Electrification and Automation business unit in Smart Infrastructure in India and will be responsible for leading costing team. As an active member you would be directly responsible to ensure a high level of accuracy in product cost and ensure proper product cost controlling. You would be leading four-to-five-member team responsible for topics related to product costing, cost controlling and various SAP masters related to factory function. The key deliverables and responsibilities would be the following: Product Costing Directs and participates in Product costing & controlling of medium voltage product. Annual cost (TCE) update and analysis for NX Tools(NXAIR products). Annual cost (TCE) update and analysis for channel partner products Experience in localization topic. EVA calculation and preparation of business case. Co-ordinate with Global Product Care / R&D teams for approvals of identified productivity measures. Controlling activities like Order cost controlling and activities related to OCC, MAP tracking, Order analysis, COPA analysis etc. Handling internal and external stakeholders including Audit / agencies, headquarters, support function etc. Internal order creation & analysis. Material cost, Cost center planning & Regulative working for FTA. Pre-bid order analysis and cost optimization for strategic orders. Cost benchmarking activities with HQ team for NXAIR panels & IVCB. License Fee payment working and Brand Royalty Fee working. Commodity impact working and analysis. Present monthly margin analysis to factory mgt of 5 orders from each variant dispatched from the factory in following month. Productivity Management OPW Controlling: Ensure reporting of MCP/VAM in OPW before closing date every month. 3i idea scheme Controlling: Check for new ideas, assign expert reviewers, assist implementation, get saving calculation and release awards. Monitor productivity goals and participate in reviews with local management. Conduct MCP / VAM workshops for generating measures. Update of productivity targets with HQ team Supplier cost controlling Technical checking of cost sheets / quotations for LTC and APS assembly. Periodic update of vendor costing formats and BOMs. Periodic physical verification of LTCs vs supplier quotations. SAP Master data Monitor daily ALE transfer, RN/TCN & resolve issues if any Act on GAP Analysis points from HQ team. Master correction if required. Secondary material master creation. Controlling open purchase orders, production orders, sales order, internal order, investment orders etc This role is based in Arioli, Thane Mumbai, Maharashtra where youll get the chance to work with various stakeholders in factory, proposal, order management, factory Mgt and BU Mgt. We dont need superheroes, just super minds Post-graduate in Mechanical or Electrical field from reputed institute will be preferred. 10 - 12 years of relevant experience of which at least 3 years in leading teams Experience in a factory costing role with a medium to large size manufacturing organization (preferred in handling engineered products), significant experience working in a multi-national environment and in a matrix organization. Extensive knowledge of product costing and medium voltage products ERP (SAP) and Finance systems knowledge Required Professional Competencies o Leadership & Management Proven track record of exemplary leadership capabilities with demonstrated ability to drive results. Strong strategic mindset with experience in guiding teams toward exceptional performance outcomes. Ability to develop and mentor team members while fostering a collaborative work environment o Operational Excellence Exceptional ability to prioritize and manage multiple complex initiatives simultaneously. Strong analytical skills with expertise in developing and maintaining comprehensive reporting frameworks. Demonstrated success in meeting critical deadlines and deliverables while maintaining high quality standards o Personal Attributes Self-motivated professional with proven ability to work autonomously and take initiative. Excellence in building and maintaining strong professional relationships across all organizational levels. Outstanding interpersonal and communication skills with the ability to influence and engage stakeholders o Team Collaboration Proven track record of fostering inclusive and high-performing team environments. Demonstrated ability to promote knowledge sharing and cross-functional collaboration. Experience in leading teams to consistently exceed performance expectations and deliver superior results

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 2-5 years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker Tempus Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 2 years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker Tempus Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language .

Skills/Experience: Proficient in STA timing fixes, ECO and Synthesis of complex SOCs at Sub system level, Block level and Chip level. Tools: Design compiler, Prime time, Tempus Experience (years) : 3+ Year Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

What You ll Be Doing: Contribute towards developing IC Validator DRC, LVS, Fill and PERC runsets Collaborate with R&D team on technologies/solution roadmaps to help them focus on the most critical design challenges Work with other Synopsys field teams, ensuring overall consistency of IC Validator solutions and that they meet customer needs. What You ll Need: Should be a graduate engineer (2024/2025) in Electronic Engineering, Computer Science. Familiarity with physical verification tool like IC Validator, Calibre, PVS or any other PV tool Understanding of DRC, LVS, Fill and multi-patterning concepts Excellent problem-solving skills Understanding of physical design layouts Good knowledge of scripting languages like Python, TCL or Perl Key Program Facts: Program Length: 12 months Location: Hyderabad Working Model: On-site Full-Time/Part-Time: Full-Time

What You'll Be Doing : - In this position, you will expect to lead all block/chip level PD activities. - PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. - Work in collaboration with design team for addressing design challenges. - Help team members in debugging tool/design related issues. - Constantly look for improvement in RTL2GDS flow to improve PPA. - Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. - Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. Minimum Qualifications : - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. What We Need To See : - Strong experience in Physical Design. - Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. - Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. - Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. - Well versed with timing constraints, STA and timing closure. - Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. - Ability to multi-task and flexibility to work in global environment. - Good communication skills and strong motivation, Strong analytical & Problem solving skills. - Proficiency using Perl, Tcl, Make scripting is preferred. - Widely considered to be one of the technology worlds most desirable employers, offers highly competitive salaries and a comprehensive benefits package.

Job Title: Stores Incharge Location: Hathnoora Industry: Building Materials / AAC Blocks Manufacturing Experience: 2 3 Years in Stores Management (preferably in manufacturing or construction material industry) Job Summary: We are looking for a proactive and detail-oriented Stores Incharge for our AAC blocks manufacturing plant located in Hathnoora . The ideal candidate will have 2 3 years of experience in managing inventory, materials handling, and store operations, preferably in a similar industrial setup. Key Responsibilities: Manage the day-to-day operations of the store, ensuring proper receipt, storage, and issuance of materials. Maintain accurate inventory records using ERP or manual systems. Conduct regular stock audits and physical verification of inventory. Ensure timely and correct documentation of inward and outward materials (GRN, issue slips, return slips). Coordinate with purchase and production teams to ensure material availability as per requirements. Maintain minimum stock levels and raise material requisitions when required. Ensure proper labeling, binning, and storage of materials to avoid damage or mix-up. Comply with safety and housekeeping standards in the stores area. Prepare reports on inventory levels, consumption, and stock movement for management review. Handle dispatch of finished goods and maintain dispatch records when necessary. Qualifications and Skills: Graduate / Diploma in any discipline (preferred in Logistics, Supply Chain, or related field) 2 3 years of experience in stores/inventory management in a manufacturing or construction materials environment. Knowledge of storekeeping practices and inventory control methods. Familiarity with ERP systems or inventory management software. Basic knowledge of MS Office (Excel, Word). Good organizational and communication skills. Ability to work independently and take initiative. Preferred Candidate Profile: Candidates with prior experience in AAC blocks manufacturing or similar construction material plants will be preferred. Candidates residing near Hathnoora or willing to relocate are encouraged to apply.

Skills/Experience: Hands-on experience in complex SOC/sub-systems implementation using Innovus & Fusion Compiler. Proficient in top-down floorplan and Power Grid methodologies. Experience in signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff. Successful track records of taping out complex IPs & SoCs at 16/10/7/5 nm Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus . Automation and programming-minded, coding experience in Tcl/Tk/Perl. Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

• Responsible for high performance microprocessor blocks RTL to GDSII implementation • Perform block level synthesis, floor-planning, placement and routing. • Close the design to meet timing, power budget and area. • Implement ECO's to address functional bugs and timing violations. • Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC.. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL ,SKILL and/or TCL

Position: Financial Reporting & Consolidation Support Title: Deputy Manager / Manager Unit: Finance & Accounts Place: Guwahati (RO), Assam Credentials: Chartered Accountant Responsibilities: Preparation of Balance Sheet and Profit & Loss Statement Analysis of Quarterly variances of Balance sheet and Profit & Loss Analysis of Inventory and valuation of finished goods IndAS Accounting of lease, Employee Loan, Borrowings etc Coordinating Internal and Statutory Audits Ensuring timely completion of quarterly and annual audits Monitoring of Capex and capitalization in SAP including WBS Creation etc. Fixed Assets Deprecation calculation through SAP Preparation of Reports on Asset for different stack holder including Audit. Physical verification of Assets of NE Plants

You will be responsible for performing chip-level floorplanning, partitioning, timing budget generation, and power planning. Additionally, you will execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation. Your duties will also involve handling block-level implementation from netlist to GDSII, driving timing closure for high-frequency blocks, and managing blocks with high instance counts (1M+). Moreover, you will ensure signoff closure for timing (including SI and OCV), power, IR drop, and physical verification, applying signal integrity (SI) prevention and fixing methodologies, and conducting layout edits and physical design optimizations. Furthermore, you will be expected to automate design tasks and manage UNIX-based environments. Your primary skills should include chip-level and block-level physical design expertise, hands-on experience with Synopsys ICC and PrimeTime, proficiency in signoff closure for timing, power, IR, and physical verification, a strong understanding of SI and OCV impacts and mitigation strategies, experience with high-frequency designs and large instance count blocks, and proficiency in layout editing techniques. Your secondary skills should encompass familiarity with Mentor Olympus and Atoptech toolsets, experience in design automation, proficiency in UNIX systems, and scripting knowledge in Tcl and/or PERL. As for educational qualifications, a Bachelors or Masters degree in Electrical Engineering, Electronics, VLSI, or a related field is required.,

Eximietas is currently seeking Senior Physical Design Leads/Managers with over 10 years of experience for a position in Visakhapatnam. Qualifications: - Minimum of 10+ years of experience in Physical Design using mainstream P&R tools - Bachelors or Masters Degree in Electronics, Electrical, Telecom, or VLSI Engineering Responsibilities: - Work on designs using 10nm/7nm/5nm or lower nodes with various customers to meet performance, area, and power targets - Develop flow and methodology for placement, CTS, and routing - Provide training and technical support to customers Required Expertise: - Strong background in place & route flow, including placement guidelines, clock-tree synthesis, routing, and timing optimizations - Experience in hierarchical designs and/or Low Power implementation is a plus - Familiarity with Synthesis, floor plan design, Static Timing Analysis, and Physical Verification (DRC/LVS/DFM) Interested candidates are encouraged to send their resumes to maruthiprasad.e@eximietas.design.,

As a Physical Design Engineer with 4+ years of experience, you will be responsible for Netlist2GDSII Implementation including Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, and Physical Verification. Your expertise should cover Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. Proficiency in programming languages like Tcl, Tk, and Perl is essential for this role. You should have hands-on experience with Synopsys and Cadence tools such as Innovus, ICC2, Primetime, PT-PX, and Calibre. Being well-versed in timing constraints, STA, and timing closure will be crucial for successful execution of projects. Your role will require inspirational leadership, effective communication skills, and the ability to collaborate in a global environment. Overall, your responsibilities will revolve around ensuring the successful implementation of physical design tasks, adhering to project timelines, and maintaining high quality standards throughout the process. Your contributions will play a key role in the development of cutting-edge semiconductor products.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to create a smarter, connected future for all. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. You should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 4+ years of Hardware Engineering experience, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. We are seeking bright ASIC design engineers with excellent analytical and technical skills to be part of a fast-paced team responsible for delivering Snapdragon CPU design for high-performance SoCs in sub-10nm process for Mobile, Compute, and IOT market space. In this role, you will participate in projects involved in the development of ASICs, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will create design experiments, perform detailed PPA comparison analysis, work closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Key Responsibilities: - Develop Place & Route recipes for optimal PPA - Tabulate metrics results for analysis comparison - Complete ASIC flow with low power, performance, and area optimization techniques - Experience with STA using Primetime and/or Tempus - Proficient in constraint generation and validation - Knowledge of multiple power domain implementation with complex UPF/CPF definition - Formal verification experience (Formality/Conformal) - Skills in Perl/Tcl, Python, C++ - Strong problem-solving and ASIC development/debugging skills - Experience with CPU micro-architecture and their critical path - Low power implementation techniques experience - High-speed CPU implementation - Clock Tree Implementation Techniques for High Speed Design Implementation - Exposure to Constraint management tool and Verilog coding experience Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please email disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. Qualcomm expects its employees to comply with all applicable policies and procedures, including security and confidentiality requirements. For more information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is seeking a passionate and skilled Hardware Engineer to join our Engineering Group. As a Hardware Engineer at Qualcomm, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on a wide range of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and deliver innovative solutions. To be considered for this role, you should hold a Bachelor's degree, Master's degree, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field, along with 1-3+ years of Hardware Engineering experience. We are particularly interested in individuals with ASIC design expertise and strong analytical skills. This is a fantastic opportunity to contribute to the development of Snapdragon CPU design and high-performance SoCs in the Mobile, Compute, and IOT market space. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be required to conduct detailed analysis to improve results, optimize Performance, Power, and Area (PPA), and collaborate closely with various teams to achieve project goals. Proficiency in tools such as FC, Innovus, Primetime, Tempus, and languages like Perl, Tcl, Python, and C++ is highly desirable. Your role will involve developing Place & Route recipes for optimal PPA, managing constraints, and ensuring the implementation of low power techniques. Experience with CPU micro-architecture, clock tree implementation, Verilog coding, and formal verification will be valuable assets. Strong problem-solving skills and a dedication to ASIC development and debugging are essential in this role. Qualcomm is an equal opportunity employer committed to providing a supportive and accessible work environment for individuals with disabilities. If you require accommodations during the application process, please contact us at disability-accommodations@qualcomm.com. We expect all employees to adhere to company policies and procedures, including maintaining the confidentiality of proprietary information. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes through our Careers Site. For further inquiries about this position, please reach out to Qualcomm Careers.,

This role is for a Physical Design Engineer to join a team working on projects with GHz frequency ranges and cutting-edge technologies. The ideal candidate will be responsible for the full physical design flow, from synthesis to physical verification, at both the full-chip and block levels. Responsibilities Perform Physical Design at the full-chip or block level. Handle the entire design flow from Synthesis to Place and Route (PnR) . Ensure Physical Verification closure of SoCs/sub-chips. Work on projects utilizing advanced technology nodes. Skills Strong skills in Physical Design . Expertise in the full design flow, including Synthesis and Place and Route (PnR) . Proficiency in Physical Verification closure . Qualifications A B.Tech. or M.Tech. degree is required for this position.

He/She should be able to do top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Timing closure on DDR2/DDR3/PCIE interfaces. Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs. Role: Physical Design / Layout Engineer Industry Type: Electronic Components / Semiconductors Department: Engineering - Hardware & Networks Employment Type: Full Time, Permanent Role Category: Hardware Education UG: Any Graduate PG: Any Postgraduate

You will be joining Micron Technology's HBM Team in Hyderabad, India as a Layout Design Engineer. In this role, you will be responsible for designing and developing critical analog, mixed-signal, custom digital blocks, and providing full chip level integration support. Your expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is essential for this position. You will work on intensive applications such as artificial intelligence and high-performance computing solutions, specifically focusing on High Bandwidth Memory. Your responsibilities will include layout verification such as LVS/DRC/Antenna, quality checks, and documentation ensuring on-time delivery of block-level layouts with acceptable quality. Additionally, you will lead junior team members, contribute to effective project management, and communicate effectively with global engineering teams. To be successful in this role, you should have 8 to 15 years of experience in analog/custom layout design in advanced CMOS processes across various technology nodes. Your hands-on experience with critical blocks like Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc., will be valuable. Understanding analog layout fundamentals, design constraints, and layout effects on circuits is crucial for this position. You should possess excellent command and problem-solving skills in physical verification of custom layout, multiple tape-out support experience, and the ability to manage multiple layout projects while ensuring quality checks are performed at all stages of layout development. Strong verbal and written communication skills are necessary to collaborate effectively with global teams. As a Layout Design Engineer at Micron Technology, you will play a key role in developing groundbreaking technologies that enrich life by transforming how the world uses information. Micron is an industry leader in innovative memory and storage solutions, driving advancements in artificial intelligence and 5G applications. If you are highly motivated, detail-oriented, and passionate about IC layout design, this opportunity is for you. Education requirements for this position include a BE or MTech in Electronic/VLSI Engineering. If you are ready to be part of a visionary team that is shaping the future of information technology, visit micron.com/careers to learn more and apply. Micron Technology, Inc. strictly prohibits the use of child labor and complies with all applicable laws, rules, regulations, and international labor standards. For assistance with the application process or accommodations, please contact hrsupport_india@micron.com.,

Job description Role & responsibilities Senior Associate-Aerodrome Safeguarding will be responsible for Delivering DGCA Orders respective obstacle owner issued as per Aircraft Rules 1994 to and other relevant activities. Assisting survey team in rendering activities w.r.t. Periodic Survey, Physical Verification as per aircraft Rules 1994, Site verification NOC cases. Document Control. Delivering DGCA Orders respective obstacle owner issued as per Aircraft Rules 1994 to and other relevant activities. Assisting survey team in rendering activities w.r.t. Periodic Survey, Physical Verification as per aircraft Rules 1994, Site verification of height clearance NOC cases. Document Control- Upkeep of Soft and Hard Copies of Correspondences made with obstacle owners, stakeholders, DGCA, AAI and other CIVIC agencies. Preferred candidate profile ITI Trade Surveyor / Diploma in Civil Engineering / Surveying or Graduate in any discipline. Knowledge of Annex 14, MS Office is desirable. Driving License Mandatory (must be 3-year-old)

You are a highly reputable and well-established CA firm specializing in direct and indirect taxation, statutory audit, bank audit, stock audit, ASM audits, revenue audits, and physical verification. With a dedicated team of experienced professionals, you have built a strong reputation for delivering exceptional client service and providing valuable insights to a diverse range of businesses. You are currently seeking highly motivated and dynamic individuals to join your team as CA Articles. As an Article Trainee, the selected candidates will have the opportunity to gain hands-on experience in various areas of accounting, auditing, taxation, and consulting. This is an excellent opportunity for candidates who are eager to kick-start their careers in the field of chartered accountancy and are looking to learn from industry experts. Responsibilities will include assisting in conducting statutory audits, including preparation of financial statements and audit documentation, supporting the team in conducting bank audits, stock audits, ASM audits, and revenue audits, participating in physical verification of assets and inventory, assisting in the preparation and filing of tax returns, engaging in tax planning and advisory services for clients, researching and staying up-to-date with relevant tax and accounting regulations, and collaborating with team members on various assignments and projects. The benefits of joining the team include exposure to a wide range of clients and industries, mentorship and guidance from experienced professionals, valuable hands-on experience in various areas of accounting, auditing, and taxation, opportunity to develop essential professional skills, competitive stipend and potential for growth within the firm, and professional development and training opportunities. If you are enthusiastic about building a successful career in chartered accountancy, please submit your detailed resume, along with a cover letter at [goelradhey@yahoo.com]. Please note that only shortlisted candidates will be contacted for further assessment and interviews. Embark on a rewarding journey towards professional growth and success in the exciting field of chartered accountancy by joining the team!,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems in order to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. This position is focused on floor-planning expertise at both block and top levels for industry-leading CPU core designs, emphasizing scalability and achieving aggressive Power, Performance, and Area (PPA) targets. Working on cutting-edge technology nodes and applying advanced physical design techniques to enhance CPU performance and efficiency is a key aspect of this role. Key responsibilities include driving floorplan architecture and optimization in collaboration with PD/RTL teams, engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams, partnering with EDA tool vendors and internal CAD teams for improved design efficiency, making strategic trade-offs in design decisions to achieve optimal PPA outcomes, and ensuring end-to-end Physical verification closure for subsystem. The ideal candidate will have experience in physical design including floor-planning, placement, clock implementation, and routing for complex, big, and high-speed designs. Knowledge of physical synthesis and implementation tools such as Cadence Innovus/Genus and Synopsys Fusion Compiler is preferred, along with a good understanding of CMOS circuit design, static timing analysis, reliability, and power analysis. Strong collaboration skills, innovative thinking for power and performance improvements, scripting skills, and expertise in Physical Verification flow are required. Preferred skills for this role include clock implementation, power delivery network design choices, process technology knowledge, experience in flow and methodology development, hands-on experience with Synthesis, DFT, Place and Route, and Timing and Reliability Signoff. Interaction with design and architecture teams, working with sub-micron technology process nodes, and prior experience in flow and methodology development are advantageous. Minimum qualifications include a Bachelor's degree in Electrical/Computer Engineering, 8+ years of direct top-level floor-planning experience, a strong background in VLSI design, physical implementation, and scripting, as well as experience working with industry-standard Synthesis and Place and Route tools. Self-motivation, time management skills, and a commitment to abide by all applicable policies and procedures are expected from applicants. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes. For more information about this role, please contact Qualcomm Careers.,

The role involves conducting internal audits of purchase, accounts, and inventory processes at manufacturing plant sites. You will assist in preparing audit reports and presenting findings to senior management or clients. Identifying areas of process improvement, cost-saving, and control gaps will be a key responsibility. You are expected to verify adherence to company policies, statutory norms, and accounting standards, and perform physical verification of stock, fixed assets, and other plant records. Supporting the implementation of internal controls and risk mitigation strategies, coordinating with plant teams, vendors, and client accounts departments, documenting audit observations, and following up on corrective actions are essential tasks. Ensuring the timely completion of assigned audit tasks and reporting is crucial. Preferred candidates should be comfortable working at a manufacturing plant location. For the Nashik/Indore location, the eligibility criteria include a qualification of M.Com/B.Com and 1 to 2 years of experience in Purchase/Accounts/Auditing. For the Jabalpur location, the preferred qualifications are CA Inter/MBA/M.Com with 2 to 3 years of experience in Purchase/Accounts/Auditing. The job types available are full-time and permanent. Benefits for this position include food provided. The work location is in person. (Note: No headers will be previewed in the final JD),

JOB Description: WE are At Synopsys, we pioneer innovations that shape our connected world. Our technology powers the Era of Pervasive Intelligence, from self-driving cars to AI. As leaders in EDA tools, chip design, verification, and IP integration, we enable the creation of high-performance silicon chips and software. Join us to drive the future with continuous technological innovation. About You: You are a talented and dedicated Senior Layout Design Engineer specializing in analog and mixed-signal (A&MS) integrated circuits. You excel in collaborative environments, working seamlessly with cross-functional teams to drive technological innovation. Your meticulous attention to detail and unwavering commitment to quality are hallmarks of your work. You are constantly striving to enhance layout design methodologies and best practices, utilizing your profound knowledge of semiconductor process technologies and industry-standard EDA tools. Your exceptional problem-solving abilities, effective communication, and strong teamwork make you an indispensable asset. What Youll Be Doing: Develop and implement layout designs for A&MS integrated circuits. Optimize layouts using industry-standard EDA tools. Perform physical verification and design rule checks. Participate in Layout reviews and provide feedback. Collaborate with circuit designers on specifications and constraints. Enhance layout design methodologies and best practices. Stay updated with industry trends in A&MS layout design. The Impact You Will Have: Ensure high quality and performance of A&MS integrated circuits. Drive innovation with cutting-edge layout designs. Improve manufacturability and reliability through meticulous design. Contribute valuable feedback during design reviews. Foster continuous improvement in design methodologies. Mentor junior engineers by sharing your expertise. Show more Show less