Memory Layout Engineer

Location Bangalore -

To work on development of embedded memory compilers ( SRAM, ROM, RF).

- Architecture exploration and choosing one based on PPA requirements.

- Schematic design and simulations

- Margin and characterization simulations

- Critical path modeling and optimization

- Interface with layout team to define the floor plan and layout guidelines for schematics. Layout review to get optimum design.

- Interface with char team to define measurement points needed for timing data generation.

- Running robustness checks on the compiler.

- Running equivalence verification (ex: ESPCV)

Experience/Skills required

- Experience in design of emJob responsibility: bedded memory compilers

- Understanding of memory architectures and the tradeoffs involved.

- Sound fundamentals in CMOS basics and custom CMOS Circuit design nodes.

- Good understanding of bitcell operation and different assist techniques required in advanced - Familiar with complete memory design ie architecture definition, circuit design, physical design, timing char and- design kit development

EDA

Perl,shel

- B.E. / B.Tech / M.E. / M