Memory Layout Engineer

We are seeking a highly skilled and experienced Memory Layout Engineer to join our team. The ideal candidate will have hands-on expertise in designing and integrating layouts for advanced memory blocks across leading-edge process technologies. You will play a critical role in developing and verifying memory compilers with a strong focus on ultra-deep sub-micron layout challenges.

Key Responsibilities:

Memory Building Block Layout Design:

Hands-on experience with designing layouts for essential memory components such as:

Control and Digital logic

Sense amplifiers

Bit-cell arrays

Decoders

Process Technology Expertise:

Proven experience in working with advanced process nodes, including:

16nm, 14nm, 10nm, 7nm, 5nm, 3nm and FinFET technologies.

Physical Verification:

Experience or strong interest in developing memory compilers, addressing layout-related issues, and ensuring optimization.

Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout

Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc.

Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area

Excellent hands-on experience in industry standard layout and verification tools in a Linux environment of Cadence and Mentor EDA tools. Power user of VirtuosoXL

Excellent Leadership skills and Mentor & guide team members in execution of Layout and review their work outputs for quality and delivery

Excellent communication skills and proactive at work

This role offers an exciting opportunity to work on cutting-edge technologies with a team of experts. If you are passionate about memory layout design and thrive in a collaborative, innovative environment, we encourage you to apply!

Qualifications :-

Location

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