2783 Verilog Jobs - Page 20

RTL/Integration- Design Engineer Work Location : Bengaluru, Whitefield Qualification : 5-10 years full-time experience in IP hardware design Mode of interview : Virtual Availability to join: candidates who can join in 30-45 Days are preferred. Normal Working Hours, 5 days a week Work Mode : Work from Office The Project and role : As a member of the Computing and Graphics group , you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. The Person: The ideal candidate will have experience developing RTL for IP or subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. Key Responsibilities: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up Preferred Experience: Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management techniques Power Gating, Clock Gating Experience with embedded processors and data fabric architectures (NoC) Functional Skills Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer Engineering/Electrical Engineering

Job Description Primary Duties & Responsibilities Architect, design, implement and test HDL modules for the payload following best practices such as efficiency, maintainability, and testability. Gather, define, and document requirements to meet existing and anticipated needs for payload systems. Develop, analyze, and review data to validate and verify the system meets specifications and design requirements. Implement real-time control algorithms and data processing routines to meet mission-critical performance requirements. Work closely with the software and hardware engineers to integrate and develop formal design verification and validation plans and perform or oversee testing. Maintain high-quality documentation of the entire design. Develop user manuals and troubleshooting guidelines for end-users. Ensure that the FPGA/RTL design meets industry standards. Work with cross-functional global teams with external stakeholders. Education & Experience Bachelors / master's degree in engineering. Minimum 5 years of experience in Firmware Development and FPGA development. Strong understanding of FPGA development tools, synthesis, simulation, and verification process. Experience with Intel-based SoCs, Quartus Prime, Modelsim, NIOS, etc. Proficient in FAGA designing and RTL(verilog) programming. Strong experience in the FPGA design process and writing device drivers in VHDL and or Verilog-embedded applications on FPGAs. Skills Experience with designing state machines and hardware interfacing with the understanding of high-speed communication interfaces (SPI, I2C, UART, and LVDS). Experience with software/firmware verification with test benches to verify design logic and generate high-quality documentation of the design and test results. Experience working in the hardware lab with knowledge of electronic equipment such as multimeters, function generators, oscilloscopes, logic analyzers, etc. Familiarity with digital signal processing (DSP) and high-speed data interfaces. Knowledge of how to optimize for memory/timing/power under resource constraints. Knowledge of understanding hardware design and SoC's specific schematics. Must be hard-working with good communication skills. Must be able to work both independently with minimal guidance, as well as part of a team. Be flexible and ability to excel in a cross-organizational, cross-cultural, global team environment. Good to have knowledge of c/c++/python/shell programming. Experience working on multiple stages of the product development lifecycle (project initiation, design completion, release, and maintenance with version control) Working Conditions Should be flexible to work outside of business hours. The work mode of Finisar India is Hybrid i.e. 3 days at office. Culture Commitment Ensure adherence to company’s values (ICARE) in all aspects of your position at Coherent Corp.: I ntegrity – Create an Environment of Trust C ollaboration – Innovate Through the Sharing of Ideas A ccountability – Own the Process and the Outcome R espect – Recognize the Value in Everyone E nthusiasm – Find a Sense of Purpose in Work Coherent Corp. is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. Finisar India (Subsidiary of Coherent Corp) is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to gender identity, sexual orientation, race, color, religion, national origin, disability, or any other characteristic protected by law. About Us Coherent is a global leader in lasers, engineered materials and networking components. We are a vertically integrated manufacturing company that develops innovative products for diversified applications in the industrial, optical communications, military, life sciences, semiconductor equipment, and consumer markets. Coherent provides a comprehensive career development platform within an environment that challenges employees to perform at their best, while rewarding excellence and hard-work through a competitive compensation program. It's an exciting opportunity to work for a company that offers stability, longevity and growth. Come Join Us! Note to recruiters and employment agencies: We will not pay for unsolicited resumes from recruiters and employment agencies unless we have a signed agreement and have required assistance, in writing, for a specific opening. LinkedIn

Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Principal Engineer,RTL Department Engineering Location Noida Remote No Requisition ID 20019236_2025-03-01

As an RTL/FPGA Design Engineer in the VLSI domain, you will play a crucial role in developing FPGA-based products. With a focus on RTL programming using Verilog/System Verilog or VHDL, you will be responsible for optimizing RTL code to meet timing requirements and on-chip resource constraints. Your expertise in FPGA Development Tools such as Quartus, Modelsim, Vivado, Xilinx ISE, and Libero will be essential in ensuring the successful completion of projects. Your responsibilities will include functional verification using Verilog/System Verilog or VHDL, system architecture design, and testing/troubleshooting of hardware components. Additionally, you will be required to support all phases of FPGA-based product development activities, demonstrating a strong understanding of FPGA design flow/methodology and IP integration. To excel in this role, you should hold a BE/B.Tech or ME/M.Tech degree in Electronics/Electronics & Communication or Electronics/VLSI Design from a recognized university. Proficiency in Verilog/SystemVerilog or VHDL for design and verification is essential, along with knowledge of protocols like SPI, I2C, UART, and AXI. Familiarity with tools such as Quartus II, Questasim, Modelsim, ISE, Vivado, and libero will be advantageous. As a self-motivated individual, you should be eager to learn and contribute effectively within a team-oriented environment. Your ability to prioritize tasks, solve problems creatively, and write clean code following coding guidelines will be highly valued. If you are passionate about working in a dynamic and innovative setting, we encourage you to apply for this exciting opportunity in Ahmedabad or Bangalore. Join us and be a part of our vibrant team dedicated to pushing the boundaries of VLSI design and FPGA technology. Apply now to explore this role further and take the next step in your career growth.,

Job Description: As a Technical Developer at Five Feed Learning Solutions Pvt. Ltd., you will be responsible for various aspects of FPGA and RTL design. You should possess good communication skills and analytical problem-solving capabilities. Your role will involve hands-on experience in FPGA/RTL Design using Verilog HDL, Tanner, Vivado ISE/Xilinx ISE, Modelsim, and Synplify Synopsys. A strong knowledge of VLSI Circuit designs and parameter synthesis is essential. Knowledge of TCAD, HSPICE, and PSPICE will be advantageous. Your responsibilities will include RTL design, verification, FPGA partitioning and implementation, as well as lab-based bring up of the SoC on FPGAs. Recent FPGA experience, including implementation, synthesis using Synplify, and timing closure with Vivado/ISE, is required. You should be able to architect, implement, and verify modules for FPGA interconnect. Proficiency in Verilog, Perl, and Make is expected. You should have expertise in both simulation-based verification and lab-based debug skills on FPGAs. Qualifications: - Graduation in B.E, B.Tech - Post Graduation in M.E., M.Tech VLSI Perks & Benefits: - Salary: Rs 2.5 Lacs - 4 Lacs p.a - Key Skills: Custom Coding, Technical Support, VLSI, Modelsim, Verilog, FPGAs, Perl, Synplify, Vivado/ISE, Xilinx ISE - Industry: Education / Training - Number of Positions: 2 Recruiter Profile: Recruiter Name: Not specified Email Address: hiringteam.3@fflspl.com Contact Company: Five Feed Learning Solutions Pvt. Ltd. Reference ID: FFLSPL/Feb-2025/189-92,

As a Verification Engineer, you will be responsible for developing and implementing comprehensive verification plans using industry-standard methodologies such as UVM. Your role will involve designing and writing robust verification environments (testbenches) to achieve high code coverage. Utilizing simulation tools like ModelSim, Cadence Incisive, and Synopsys VCS will be essential for verifying RTL functionality. You will play a crucial part in debugging and analyzing verification failures to identify the root cause of design issues. Collaboration with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements will be a key aspect of your responsibilities. Additionally, your involvement in code reviews and ensuring adherence to verification coding standards will be significant. Staying up-to-date with the latest verification tools and methodologies will be crucial for your continuous growth and success in this role. Qualifications required for this position include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (a Master's degree is a plus). You should have 5-7 years of experience in design verification for ASICs or SoCs. A strong understanding of digital design principles, including combinational logic and sequential logic, is essential. Your proven ability to develop and debug complex verification environments, proficiency in Verilog or VHDL, and experience with verification methodologies like UVM will be highly valued. Experience with simulation tools and scripting languages such as Python and Perl would be advantageous. Excellent analytical and problem-solving skills, along with strong communication and collaboration abilities to work effectively in a team environment, are qualities that will contribute to your success in this role.,

You will be responsible for designing and developing Debug IPs focusing on CoreSight IP design. Your role will involve ensuring that the Debug IPs meet the required specifications and performance standards. You will utilize your expertise in RTL design using Verilog and/or SystemVerilog for complex SoC development. Additionally, you will apply your knowledge of Arm-based designs and/or Arm System Architectures to develop and optimize IPs. Collaboration with cross-functional teams, SoC integration & Architecture teams is essential to ensure successful IP delivery within specified timelines. Implementing rigorous verification processes to ensure that the IPs meet all functional and performance requirements is a key aspect of the role. To qualify for this position, you should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design for complex SoC development using Verilog and/or SystemVerilog is required. A strong understanding of Arm-based designs and/or Arm System Architectures is essential. Proficiency in IP design, verification, and delivery, with a focus on Debug IPs, is also a key requirement. Excellent communication and collaboration skills are necessary to effectively work with cross-functional teams. Preferred skills for this role include experience with CoreSight based Debug IP design and strong problem-solving and analytical skills.,

Qualcomm India Private Limited is a company of inventors that unlocked 5G, leading to rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. In the Invention Age, inventive minds with diverse skills, backgrounds, and cultures are needed to turn 5G's potential into world-changing technologies and products. As part of the successful engineering team at Qualcomm, whose deliveries are present in billions of mobile, compute, and IoT products globally, you will play a crucial role. This position, based in Qualcomm's Bangalore office, focuses on Low Power controller IP cores and subsystem digital design for industry-leading Snapdragon SoCs in mobile, compute, IoT, and Automotive markets. Your responsibilities will include micro-architecture and RTL design for Cores/subsystems, working closely with various teams for design convergence, enabling SW teams to utilize HW blocks, qualifying designs using static tool checks, and reporting progress against expectations. Preferred qualifications for this role include 4 to 10 years of experience in digital front-end design, expertise in RTL coding in Verilog/SV/VHDL, familiarity with UPF and power domain crossing, experience in synthesis, logical equivalence checks, and netlist CLP, proficiency in various bus protocols, low power design methodology, formal verification, and post-Si debug. Additionally, expertise in scripting languages like Perl/TCL/Python, database management flows, and effective communication skills are desired. Minimum qualifications entail a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of relevant experience, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. The company expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Qualified applicants are encouraged to apply, and staffing/recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes. For more information about this role, please contact Qualcomm Careers.,

As an AMS Verification Engineer, you will be responsible for working on Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Your role will involve hands-on experience with AMS simulation environments using tools such as Cadence, Synopsys, or Mentor. It is essential to have a solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Your expertise in Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling will be crucial for block-level and chip-level AMS verification. This includes top-level testbench development, self-checking testbenches, and regression suites. Exposure to SystemVerilog (SV) and UVM from an AMS perspective will be considered a plus. Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation is required. You should be fluent with Cadence Virtuoso-based analog design flow, encompassing schematic capture, simulator/netlist configuration, and SPICE simulation. Your ability to extract, analyze, and document simulation results and present findings in technical reviews is highly valued. Furthermore, familiarity with test plan development, AMS modeling, and verification methodologies is essential. You will also be involved in supporting post-silicon validation and correlating measurement data with simulations. As a valued team member, you should be team-oriented, proactive, and able to contribute effectively in a multi-site development environment.,

As part of our team working on building India's first commercial Scanning Electron Microscope (SEM) from scratch, your primary responsibility will be to design and develop the real-time beam controller on a Zynq Ultrascale+ (ARM+FPGA). You will be working on achieving a pixel clock of 20 MHz with 5 ns jitter, ensuring a blanking rise/fall time of less than 25 ns into 50. Additionally, you will implement closed-loop stage control utilizing high-resolution position feedback and update the PID at a frequency of 10 kHz. Your role will also involve streaming 16-bit detector data at a rate of 250 MB/s over PCIe to host memory. Furthermore, you will be tasked with delivering imaging algorithms such as auto-focus, auto-stigmation, and drift correction that run at 5 frames per second. To facilitate scripting and automated metrology, you will need to develop a clean and well-documented Python API. To excel in this role, you should possess at least 6 years of experience in C++17/C, Python, real-time Linux or RTOS. You should be comfortable working with FPGA toolchains like Vivado and Verilog. A strong background in DSP and control theory is essential, and you should be adept at using tools like scope probes and logic analyzers. Any prior experience with SEM, TEM, or other charged-particle systems would be considered a bonus. We are interested in learning about the most challenging technical problem you have successfully tackled and why you are excited about contributing to Bharat Atomic's mission. If you are passionate about turning first-principles physics into a manufacturable instrument and possess the required skills and experience, we encourage you to share your CV and Portfolio with us.,

As a Senior RTL Design Engineer with 3-5 years of experience, you will be based in Hyderabad. You will be required to demonstrate strong RTL (Verilog/System Verilog) skills with a focus on IP development. Your responsibilities will include verifying designs by creating simple testbenches, as well as possessing a solid foundation in logic synthesis and timing closure concepts. Additionally, you should have a good understanding of SoC architecture, AXI bus protocols, and hardware debug processes. Experience with Xilinx FPGAs, Vivado tool flows, and micro-architecture development will be considered a plus. If you meet the specified requirements and are interested in this opportunity, please submit your updated resume to janagaradha.n@acldigital.com.,

You will be a member of the FPGA development team designing and developing complex FPGAs for use in state-of-the-art embedded systems. As an FPGA Senior Design Engineer / Module Lead, you will be involved in requirements gathering, architecture and detailed design of FPGAs, coding, code walk, development of verification and validation plans, documentation of design, verification / validation, user guides, etc., technical reviews, maintaining Quality standards as per the Project Quality Guidelines and mentoring team members. Experience in architecture design, development and verification of complex FPGAs is crucial for this role. You should possess excellent RTL coding skills in Verilog/VHDL and be familiar with AMD (Xilinx) / Intel (Altera) / Lattice / Microchip FPGAs. Additionally, familiarity with AMD (Xilinx) ISE, Vivado / Intel (Altera) Quartus / Lattice Diamond / Microchip Libero FPGA tools is required. Experience in Functional verification using ModelSim and familiarity with high-speed interfaces such as PCIe, SPI-4.2, SFI-4.2, Gigabit Ethernet, UTOPIA, POS PHY, USB2/3, DDR3, SPI, UART, I2C, Aurora etc. is necessary. Exposure to FPGA Static Timing Analysis and knowledge of scripting languages like TCL and Python are desired skills. You should also have knowledge of Interfacing FPGA to ADC, DACs and experience in FPGA on-chip debugging with Chipscope/ Signaltap. Test bench development in VHDL / Verilog / System Verilog and familiarity with hardware test equipment like High-Speed DSO, Logic Analyzer, Spectrum Analyzer, Network Analyzers, Traffic Generators, etc. are important aspects of this role. Understanding of high-speed Microprocessors / Micro-controllers, L2/L3 switching, TCP/IP, and other networking protocols is beneficial. Knowledge of Hardware Schematics, Quality Process, and Configuration Management tools is also required for this position. Good oral and written communication skills, strong organizational, presentation, and motivational skills are essential qualities. The ideal candidate should have 3 to 5 years of experience in FPGA Development and hold a BE / B.Tech / M.Tech degree in Electronics & Communication Engineering.,

Were hiring a talented RTL Design Engineer to join our team in Hyderabad and contribute to advanced ASIC/SoC projects. Key Responsibilities: Perform RTL integration for ASIC/SoC designs Debug CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) violations Analyze and resolve timing and CLP (Clock Level Planning) issues Apply strong digital design fundamentals in RTL development Tackle complex design problems with excellent debugging skills Requirements: 3+ years of experience in RTL design and integration Solid foundation in digital logic design Strong problem-solving and debugging abilities

Position: Design Verification Engineer Experience: 48 Years We are looking for a skilled Design Verification Engineer with hands-on experience in MIPI protocols and Display IP. For any queries or further details, feel free to reach me at karthik.adasu@Proxilera.com Responsibilities: Experience in MIPI protocol verification (e.g., MIPI DSI, CSI). Strong hands-on experience in Display IP verification and validation. Ability to develop and execute verification plans targeting display and MIPI components. Perform RTL, gate-level, low-power simulations; ensure ISO 26262 compliance. Build SystemVerilog/UVM testbenches tailored to MIPI and Display IPs. Perform simulation and debug activities for MIPI/Display-related RTL modules. Collaborate with RTL and integration teams to resolve display and MIPI interface bugs. Integrate MIPI and Display IPs into subsystem or SoC-level test environments. Implement protocol-specific checkers, monitors, and assertions. Analyze functional coverage metrics related to display pipelines and MIPI interfaces. Work closely with post-silicon and firmware teams to validate MIPI and display functionality

About the Role We are hiring for an Executive Assistant to the founders at Leap. The primary expectation from this role is to provide real leverage to the founders and make sure that they are insanely productive at what they do. Because productive founders set the benchmark for productivity and performance for the company. The charter for this role will include Perform tasks such as managing calendars, planning travel, and other relevant administrative duties. Prompt coordination among various stakeholders for both internal and external meetings. Follow up on action items and ensure timely closure of all actionables. Leading and ensuring the success of vital cross-functional initiatives with multiple stakeholders. Tracking monthly milestones and setting up reviews for the same across all functions. Ideal Persona 2+ relevant years of experience as an EA to the founder or senior leadership team. Extremely resourceful and great at problem solving. Hands-on, adept at multitasking. Exceptional organizational skills and impeccable attention to detail. High degree of professionalism in dealing with diverse groups of people, including Board members, senior executives, internal team, community leaders, donors.

Job Overview: Experience: 3-15 years Responsibilities: Verification engineer with a knowledge of IP verification or SoC integration verification Experience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL. Experience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components Experience in formal verification strategy for complex IP blocks defining properties, driving proofs and coverage closure Your key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience : Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies UVM/OVM, Formal(jasper), power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of IP or SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Porting peripheral driver software Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures. Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm

SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Developing best-in-class architecture for Analog Mixed Signal IPs and high-speed parallel PHY interface solutions for next generation NAND flash memory controllers in advanced CMOS technology nodes. Interact with cross-functional teams to define requirements/specs, conceive the optimal solution by evaluating architectures, drive implementation, closely work with layout designers in guiding and reviewing the layouts, ensure timely and high-quality deliverables, extend SOC integration support and review and provide support for post-silicon activities from IP characterization to yield improvement and RMA. Provide good technical leadership in problem solving, planning and mentoring junior and senior engineers. Propose innovative design solutions and design methodologies. Fostering innovation culture and developing efficient processes by adopting state-of-the-art technologies. Qualifications Must have Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Working experience (20+ years) in IO including 5+ years as a project leader S

Where ASIC Digital Design, Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12333 Remote Eligible No Date Posted 22/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished digital design engineer with an unyielding drive for excellence. You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems. With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR, PCIe, USB, or HBM. Your expertise extends beyond individual contribution you are equally comfortable leading and mentoring small teams, fostering an environment of collaboration and shared learning. You are adept at translating functional specifications into detailed micro-architecture and design documents, always ensuring clarity and precision. Your technical toolkit includes mastery of Verilog/SystemVerilog, and you are well-versed in industry-standard flows encompassing linting, CDC analysis, synthesis, and static timing. You re not just a technical expert; you are a proactive communicator, an enthusiastic collaborator, and a natural problem solver who takes initiative and ownership of deliverables. Your ability to adapt to a global, multi-site team environment is matched only by your commitment to continuous learning and professional growth. If you re ready to take on a pivotal role in shaping next-generation silicon IP, Synopsys is where your aspirations and impact can soar. What You ll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores. Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features. Contributing as an individual designer handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development. Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing. Leading or mentoring small teams of designers, providing technical guidance and fostering professional development. Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies. Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables. The Impact You Will Have: Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide. Elevating Synopsys reputation for technical excellence and innovation in the IP design space. Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies. Enabling customers to achieve faster time-to-market and superior silicon performance. Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth. Driving continuous improvement in design methodologies, enhancing efficiency and product quality. Supporting Synopsys mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions. What You ll Need: Bachelor s or Master s degree in Electrical Engineering, Electronics, VLSI, or related discipline. 5+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM. In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design. Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification. Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces). Familiarity with scripting languages such as Perl or Shell an advantage. Demonstrated ability to technically lead or mentor small teams of engineers. Who You Are: A collaborative team player who thrives in a multi-site, multicultural environment. An effective communicator, able to translate complex technical concepts for diverse audiences. A proactive problem-solver with strong analytical and troubleshooting skills. Self-motivated, showing high initiative and ownership of responsibilities. Adaptable and eager to learn, always seeking opportunities for personal and professional growth. Committed to fostering a positive, inclusive, and innovative team culture. The Team You ll Be A Part Of: You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores. As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design. The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Where Analog Circuit Design Specialist Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12346 Remote Eligible No Date Posted 22/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Our Silicon Design & Verification business leads the industry in enabling customers to design and verify advanced silicon chips faster and with more reliability. We develop the next-generation processes and models that optimize chips for power, cost, and performance, shaving months off project schedules for our global clientele. We believe in fostering an inclusive and diverse environment where every voice is valued and innovation thrives. You Are: You are a passionate and experienced Analog/Mixed-Signal (A&MS) Circuit Design Engineer with a track record of excellence in high-speed physical interface development. With a deep foundation in CMOS circuit design, device physics, and nanometer technologies, you thrive on solving complex challenges at the intersection of analog and digital domains. You are energized by working on industry-leading projects and are adept at architecting, designing, and validating advanced circuits such as transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends. Your expertise allows you to optimize for performance, area, and power, and you are comfortable with layout considerations and parasitic optimizations. You value diversity and inclusion, recognizing the strength that comes from varied perspectives and backgrounds. You are ready to contribute to a culture of innovation, respect, and excellence helping Synopsys remain at the forefront of the smart everything revolution. What You ll Be Doing: Designing and developing high-speed analog and mixed-signal full-custom circuit macros, including transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends for PHY IPs in advanced CMOS technologies (planar and finFET). Analyzing and implementing various analog circuit techniques to optimize dynamic/static power, enhance performance, and reduce silicon area. Collaborating with global teams to define micro-architectures from specifications and create robust simulation environments for design verification. Performing transistor-level circuit design, simulation, and troubleshooting in nanometer processes, with a focus on reliability and manufacturability. Working closely with layout engineers to optimize parasitics, ensure design closure, and address layout-dependent effects. Participating in design reviews, providing technical guidance, and mentoring junior engineers within a high-performing, diverse team. Adopting and developing automation and scripting to streamline design and verification flows, leveraging languages such as Verilog-A and others as needed. The Impact You Will Have: Advance the state-of-the-art in high-speed PHY IP development, contributing directly to next-generation technology in AI, IoT, 5G, and automotive industries. Enable Synopsys customers to achieve faster time-to-market with optimized, reliable, and high-performance silicon solutions. Drive innovation in low-power and high-speed circuit design, helping customers meet stringent power and area targets. Enhance Synopsys reputation as a global leader in silicon design and verification through technical excellence and customer success. Mentor and elevate the skills of team members, fostering a collaborative and growth-oriented culture. Contribute to a diverse and inclusive workplace, ensuring a wide range of perspectives and ideas inform our solutions. What You ll Need: BE + 5 years or MTech + 4 years of relevant experience in Electrical/Electronics/VLSI Engineering or closely related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron/nanometer methodologies. Hands-on experience in analog transistor-level circuit design for high-speed applications (Multi-Gbps, PAM4 SERDES architectures). Proficiency in SPICE simulations, reliability analysis, and optimizing for layout parasitics. Ability to micro-architect circuits from specifications, set up verification environments, and debug complex analog/mixed-signal circuits. Basic proficiency with automation/scripting languages and familiarity with Verilog-A is a plus. Experience collaborating with cross-site, multicultural teams and strong documentation skills. Who You Are: Innovative thinker with a problem-solving mindset and a passion for continuous learning. Collaborative team player who values diversity, inclusion, and open communication. Detail-oriented, quality-focused, and committed to delivering results on time. Strong interpersonal and mentoring skills, able to guide and support less experienced team members. Adaptable and resilient, comfortable working in a fast-paced, dynamic environment. The Team You ll Be A Part Of: You will join a dynamic, high-performing team dedicated to the design and development of high-speed physical interfaces for advanced semiconductor products. Our team is composed of talented engineers with deep expertise in analog and mixed-signal design, working collaboratively across multiple sites worldwide. We value innovation, knowledge-sharing, and a culture of mutual respect, enabling every team member to grow and contribute to industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Candidate must have completed 03-06 months of training in VLSI. Candidate must have knowledge about: VLSI - Design Verification VLSI - Physical Design VLSI - Hardware VLSI - Analog Circuit Analog (Memory Design/Layout) VLSI - DFT RTL

In today s world of faster and more virtualized servers, storage, and network connections, CPUs cannot keep up with the growing network processing demands. Legacy or foundational network interface cards (NICs) may deliver efficient networking however when running demanding workloads, they cause overhead that burdens CPUs, chewing into available processing power. To deploy more advanced networking capabilities a new generation of intelligent NICs are required to deliver accelerations and additional processing power to offload CPUs. The industry-leading NVIDIA SmartNICs/DPUs (Data Processing Units) provide sophisticated hardware offloads and accelerated networking, storage, security, and manageability services for modern cloud, artificial intelligence, telecommunications and traditional enterprise workloads. With unmatched RDMA over Converged Ethernet (RoCE) performance, NVIDIA SmartNICs/DPUs deliver efficient, high-performance remote direct-memory access (RDMA) services to bandwidth- and latency-sensitive applications. The NBU team in India is a new team that is growing at a fast pace. We are currently seeking an Experienced Verification Engineer with strong verification fundamentals to work in NBU ASIC team. You will join a group of hardworking engineers to implement the next innovative Networking Silicon chip. In this position, youll make a real impact in a multifaceted, technology-focused company while developing the industrys best high-speed communication devices, delivering the highest throughput and lowest latency! What you ll be doing: Be responsible for verifying the smartNIC/DPU designs, architecture and micro-architecture using advanced verification methodologies. You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. Use advanced verification methodologies like e-specman, SV-UVM etc. What we need to see: BS / MS (or equivalent experience) with 10+ years of experience in design verification. Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc. ). C/C++ programming/scripting language experience desirable. Ways to stand out from the crowd: Prior experience of smartNIC and/or high-speed interconnects. Strong debugging, problem-solving and analytical skills. Scripting knowledge (Python/Perl/shell). Good interpersonal skills and ability & desire to work as a phenomenal teammate. Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www. nvidiabenefits. com/ #LI-Hybrid

Role: Functional verification Engineer Skills: UVM,Verilog or SystemVerilog, SOC, ASIC, AMBA Bus Protocols Location: Hyderabad Experience: 4-10 yrs Open Positions: 8 Client: AMD Notice Period- Immediate - 45 Days Skills: amba,systemverilog,soc,verilog,amba bus protocols,functional verification,dv,uvm,asic

Role & responsibilities Design and Development : Develop and implement FPGA architectures and digital circuits using VHDL or Verilog. Write RTL code and testbenches to meet functional and performance requirements. Perform synthesis, place-and-route, and timing analysis to ensure design closure. Simulation and Verification : Simulate designs using tools like ModelSim, Questa, or Vivado Simulator to validate functionality. Create and execute test plans on hardware test benches to verify FPGA designs. System Integration : Collaborate with hardware, software, and system engineers to integrate FPGA designs into larger systems. Debug and troubleshoot FPGA implementations using tools like logic analyzers, oscilloscopes, and JTAG. Optimization : Optimize FPGA designs for speed, resource utilization, and power efficiency. Ensure signal integrity and timing constraints are met for high-speed interfaces. Documentation : Document design processes, specifications, and test results for compliance and future reference. Participate in design reviews and provide technical input. Continuous Improvement : Stay updated with the latest FPGA technologies, tools, and methodologies. Propose and implement improvements to design workflows and processes. Qualifications and Skills : Education : Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Experience : 4-6 years of professional experience in FPGA design, development, and verification. Proven track record of delivering FPGA-based projects from concept to production. Technical Skills : Proficiency in HDL languages (VHDL and/or Verilog/SystemVerilog). Experience with FPGA development tools such as Xilinx Vivado, Intel Quartus, or Microchip Libero. Strong understanding of digital design principles, including timing analysis, signal integrity, and data path optimization. Familiarity with high-speed communication protocols (e.g., PCIe, Ethernet, USB, JESD204B). Experience with simulation tools (e.g., ModelSim, Questa, or VCS). Knowledge of scripting languages (e.g., Python, TCL, or Perl) for automation. Familiarity with embedded systems and hardware-software co-design is a plus. Soft Skills : Strong problem-solving and analytical skills. Ability to work independently and collaboratively in a team environment. Excellent communication skills for technical discussions and documentation Preferred candidate profile Experience in a regulated industry (e.g., aerospace, defence, or medical devices). Knowledge of digital signal processing (DSP) or high-speed digital design. Familiarity with SoC architectures (e.g., Xilinx Zynq, Intel Cyclone) and IP integration. Experience with version control tools (e.g., Git, SVN).

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Our Silicon Design & Verification business leads the industry in enabling customers to design and verify advanced silicon chips—faster and with more reliability. We develop the next-generation processes and models that optimize chips for power, cost, and performance, shaving months off project schedules for our global clientele. We believe in fostering an inclusive and diverse environment where every voice is valued and innovation thrives. You Are: You are a passionate and experienced Analog/Mixed-Signal (A&MS) Circuit Design Engineer with a track record of excellence in high-speed physical interface development. With a deep foundation in CMOS circuit design, device physics, and nanometer technologies, you thrive on solving complex challenges at the intersection of analog and digital domains. You are energized by working on industry-leading projects and are adept at architecting, designing, and validating advanced circuits such as transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends. Your expertise allows you to optimize for performance, area, and power, and you are comfortable with layout considerations and parasitic optimizations. You value diversity and inclusion, recognizing the strength that comes from varied perspectives and backgrounds. You are ready to contribute to a culture of innovation, respect, and excellence—helping Synopsys remain at the forefront of the smart everything revolution. What You’ll Be Doing: Designing and developing high-speed analog and mixed-signal full-custom circuit macros, including transmitters, receivers, clocking circuits, equalizers, serializers, de-serializers, and analog front ends for PHY IPs in advanced CMOS technologies (planar and finFET). Analyzing and implementing various analog circuit techniques to optimize dynamic/static power, enhance performance, and reduce silicon area. Collaborating with global teams to define micro-architectures from specifications and create robust simulation environments for design verification. Performing transistor-level circuit design, simulation, and troubleshooting in nanometer processes, with a focus on reliability and manufacturability. Working closely with layout engineers to optimize parasitics, ensure design closure, and address layout-dependent effects. Participating in design reviews, providing technical guidance, and mentoring junior engineers within a high-performing, diverse team. Adopting and developing automation and scripting to streamline design and verification flows, leveraging languages such as Verilog-A and others as needed. The Impact You Will Have: Advance the state-of-the-art in high-speed PHY IP development, contributing directly to next-generation technology in AI, IoT, 5G, and automotive industries. Enable Synopsys customers to achieve faster time-to-market with optimized, reliable, and high-performance silicon solutions. Drive innovation in low-power and high-speed circuit design, helping customers meet stringent power and area targets. Enhance Synopsys’ reputation as a global leader in silicon design and verification through technical excellence and customer success. Mentor and elevate the skills of team members, fostering a collaborative and growth-oriented culture. Contribute to a diverse and inclusive workplace, ensuring a wide range of perspectives and ideas inform our solutions. What You’ll Need: BE + 5 years or MTech + 4 years of relevant experience in Electrical/Electronics/VLSI Engineering or closely related field. Strong fundamentals in CMOS circuit design, device physics, and sub-micron/nanometer methodologies. Hands-on experience in analog transistor-level circuit design for high-speed applications (Multi-Gbps, PAM4 SERDES architectures). Proficiency in SPICE simulations, reliability analysis, and optimizing for layout parasitics. Ability to micro-architect circuits from specifications, set up verification environments, and debug complex analog/mixed-signal circuits. Basic proficiency with automation/scripting languages and familiarity with Verilog-A is a plus. Experience collaborating with cross-site, multicultural teams and strong documentation skills. Who You Are: Innovative thinker with a problem-solving mindset and a passion for continuous learning. Collaborative team player who values diversity, inclusion, and open communication. Detail-oriented, quality-focused, and committed to delivering results on time. Strong interpersonal and mentoring skills, able to guide and support less experienced team members. Adaptable and resilient, comfortable working in a fast-paced, dynamic environment. The Team You’ll Be A Part Of: You will join a dynamic, high-performing team dedicated to the design and development of high-speed physical interfaces for advanced semiconductor products. Our team is composed of talented engineers with deep expertise in analog and mixed-signal design, working collaboratively across multiple sites worldwide. We value innovation, knowledge-sharing, and a culture of mutual respect, enabling every team member to grow and contribute to industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.