2452 System Verilog Jobs - Page 47

Qualcomm India Private Limited is currently seeking experienced Wireless Modem Hardware Model Developers to join their Bangalore Wireless R&D Hardware team. In this role, you will have the opportunity to work on Qualcomms" cutting-edge chipsets in modem WWAN IPs. Your responsibilities will include contributing to the development of flagship modem core IPs covering 5G (NR) and 4G (LTE) technologies. Additionally, you will be part of a team defining and developing next-generation multi-mode 5G modems. Your tasks will involve working on the development and verification of hardware models of modem core IPs, which are developed on the C++/SystemC platform and used as a golden reference for RTL ve...

You will be responsible for executing internal projects or small tasks within customer projects related to VLSI Frontend, Backend, or Analog design with minimal supervision from the Lead. Your role will involve working as an Individual contributor on tasks such as RTL Design, Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will be expected to analyze and complete assigned tasks within the defined domain successfully and on time with minimal support from senior engineers, ensuring quality delivery as approved by the senior engineer or project lead. Quality of deliverables is a key focus, requiring clean delivery of modules that are easy to...

As a SOC Design Verification Engineer with Python Automation Engineers at UST, you will be a key member of the verification team responsible for developing and executing verification plans for complex System-on-Chip (SoC) designs. You will collaborate closely with design and architecture teams to ensure the quality and reliability of products. Your role will involve performing functional and performance verification of SoC designs using simulation, emulation, and formal verification techniques. You will create and maintain verification environments, develop test benches, test cases, and coverage models using industry-standard tools and methodologies like UVM, SystemVerilog, and C++. Addition...

The job is based in Bangalore/Hyderabad and requires a notice period of 15 to 30 Days with a minimum experience of 4 Years. As a candidate, your key responsibilities will include developing test plans, coding and bringing up asm, c++ tests, coding and maintaining UVM test bench components, debugging regression fails, and working with protocols such as DDR, PCIE, USB, MIPI, and PCIE. The ideal candidate should have experience working on Processor based Systems or Sub-system level verification. It is preferred that you have hands-on experience with assembly, UVM, SV, C++, and have worked on developing complex test bench/models in UVM, Verilog, and System Verilog. Additionally, you should have ...

We are looking for a Senior R&D Engineer to join our prestigious Synthesis team based in Noida, supporting a variety of EDA products. If you have 4 to 12 years of experience and possess strong skills in C/C++ based software development, this role might be a perfect fit for you. Your expertise should include a solid foundation in Design Patterns, Data Structures, Algorithms, and programming concepts. You should be familiar with multi-threaded and distributed code development, ASIC design flow, as well as EDA tools and methodologies. Proficiency in Verilog, System Verilog, and VHDL HDL is a must. Additionally, you should be well-versed in Software Engineering practices and have experience in p...

As a candidate for this role, you should hold a Bachelor's degree in Electrical/Computer Engineering or possess equivalent practical experience. You should also have at least 2 years of experience working with RTL design using Verilog/System Verilog and microarchitecture, particularly in the realm of ARM-based SoCs, interconnects, and ASIC methodology. A Master's degree in Electrical/Computer Engineering would be considered a preferred qualification for this position. Additionally, experience with methodologies for RTL quality checks (such as Lint, CDC, RDC) and low power estimation, timing closure, and synthesis would be beneficial. Join a dynamic team that is dedicated to pushing boundarie...

You Are: An experienced Emulation Engineer with Zebu experience. The Work: Port ASIC and IP RTL code to emulation platforms (Zebu). Build model from released RTL. Generate loadable image(s) for target emulation platform. Run sanity tests to qualify release of the image(s). Release the emulation models to various teams doing functional validation, firmware development and design verification. Assist debug of failures with stakeholder by providing instrumented models and captured waveforms extracted from emulation model. Coordinate with EDA and third-party tools team to validate implementation flows. Heres what you need: A minimum 2 years of experience in Emulation (Zebu) using System Verilog/...

Job Description for DV You will be part of the team verifying IPs and SoCs leading to first Si success. Manage and lead a team of Verification engineers IP verification is coverage driven using latest industry standard methodologies and HVLs. Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases. Code coverage, Functional coverage and assertions are desired. ARM based SoC verification experience is an added advantage. Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus. Multiple positions with emphasis on AMS and Power aware verification. Should have worked on GLS. Key Re...

Today, ARM is well recognized as the market leader in the CPU and System IP industry and this has been achieved by consistently delivering reliable and high quality IP products. The cost of design and manufacturing is high and that warrants right first time approach for all IP and System products. Time-to-market is essential for our partners to take care of steadfast competition in the marketplace, being first would enable them to get premium value from the end products. In this context, Design Verification of CPU IPs is an exciting challenge requiring an engineering abilities that is both broad and deep. System Validation engineers in this group are responsible for driving validation specif...

: ARM CPU Verification Engineers have and develop specialist skills and knowledge and apply both hardware and software skills to the validation task. They work closely with the designers to understand various areas of the design, so that the features are thoroughly validated. This requires an insight both of the big picture at the architectural level and of the detail at the implementation level. Responsibilities: Technical Contribution as part of Project teams to deliver effective ARM CPU IPs Design and development of verification testbench and components needed for effective verification Execution of CPU DV with focus on improvement of IP quality; stress testing and bug hunting Effective c...

SE NIOR SOC VERIFICATION ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with othe...

[{"Salary":null , "Remote_Job":false , "Posting_Title":"SoC Verification Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Summary: Experience in ARM based SoC Verification. Must be familiar with bus matrix (fabric) designs, ETB, NVIC and ARM subsystems. Proficiency in SystemVerilog and UVM Experience with SoC memory sub-system, bus fabric, and DDR interfacing. Experience with standard interfaces such as DMA, PWM, WDOG, Timer etc. Experience with the AMBA- AXI/APB protocols Ability to deal with ambiguity, strong analytical and problem-solving skills. Proactive technical leadership, strong interpersonal skills and communication skills, and a...

[{"Salary":null , "Remote_Job":false , "Posting_Title":"Lead Memory Subsystem Design Verification Engineer (DDR / HBM)" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Proven hands-on experience verifying the digitallogic of DDR/HBM memory subsystems. Solid understanding of JEDEC specifications for LPDDRx/DDRx/HBMx Knowledge of DDR PHY interface (DFI) protocols and specifications. Familiarity with RAS (Reliability, Availability, and Serviceability) featuresin memory subsystems: Requirements Integrate and bring upVerification IPs (VIPs) such as DDR_PHY and memory models into UVMenvironments. Develop drivers, checkers, and scoreboards using SystemVer...

[{"Salary":null , "Remote_Job":false , "Posting_Title":"Lead DSP- SoC Verification Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Specialized in verifying DSP based SoC designs -Knowledge of Smart Cache/TCM -Familiar with Multiply and accumulate unit (MAC) -Understanding of SIMD on vector operation -Knowledge of IEEE fixed and floating points Must be familiar with ARM/RISC-V subsystems. Proficiency in SystemVerilog and UVM Capable of writing C code and working on SystemVerilog-C (SV-C) test-benches. Experience with SoC memory sub-system, LPDDR. Requirements Experience with standard interfaces such as JTAG, SPI, Ethernet, UCIe etc. Experi...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

About The Role Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test ca...

[{"Salary":null , "Remote_Job":false , "Posting_Title":"Principal SoC-GLS Verification Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Collaborate closely witharchitecture and RTL design teams to verify functional correctness of thedesign. Develop detailed test plans and set up test environments accordingly. Assist in building and enhancing verification & GLS flows, automationscripts, and regression infrastructure. Write and implement tests using assembly, C/C++, SystemVerilog based on definedtest plans. Design and implement checkers in SystemVerilog or C-based transactors tovalidate functionality. Write assertions and apply formal verifi...

PMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Computing and Graphics Group, you will help bring to life cutting-edge designs. You will lead a front-end design and integration team, working closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: The ideal candidate will have experience leading a team to develop RTL for SoC subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. KEY RESPONSIBLITIES: Design of IP and subsystems with integration of AMD a...

Understand the design specification , TB architecture Learn in IBM Fusion and Trek verification languages and tools, apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of work experience in IP, Sub-system & SOC level - Exp in creating multiple UVM/SV based env from scratch, Strong in Block Level verification Exp in developing checkers, Scoreboards, Monitors, Test plan development, Code c...

As Logic Lead, you will be responsible for design and development of Compression, Security, and sustainability features for high performance Processors chips. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature Guide and mentor junior engineers. Represent as Design Lead in various forums. Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Estimate the overall effort to dev...

About The Role JD Must have skills. Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to s...

We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team. Key Responsibilities Work closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPs Carry out floor planning, and physically aware synthesis on high-performance IPs Perform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL team Leads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions...

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills VHDL,RTL coding,Mentor DfT tools,Caden...

Skill : DV Lead/Manager Experience : 10 -15Yrs Location : AHMD/BLRE/HYD 10 to 15 years of relevant experience in IP or SOC Verification Must have experience in, developing test bench/test case using System Verilog & UVM Must have experience in functional coverage & assertions development. Experience High Speed Protocol Verification is preferrable Experience in ARM Based SOC Verification Exposure to GLS is an added advantage Experience in PCI/Ethernet/DDR Interested professionals can share your updated profile to chakradhar.marupuru@quest-global.com Current CTC : Expected CTC: Notice Period :