1868 System Verilog Jobs - Page 24

: ARM CPU Verification Engineers have and develop specialist skills and knowledge and apply both hardware and software skills to the validation task. They work closely with the designers to understand various areas of the design, so that the features are thoroughly validated. This requires an insight both of the big picture at the architectural level and of the detail at the implementation level. Responsibilities: Technical Contribution as part of Project teams to deliver effective ARM CPU IPs Design and development of verification testbench and components needed for effective verification Execution of CPU DV with focus on improvement of IP quality; stress testing and bug hunting Effective c...

SE NIOR SOC VERIFICATION ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with othe...

[{"Salary":null , "Remote_Job":false , "Posting_Title":"SoC Verification Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Summary: Experience in ARM based SoC Verification. Must be familiar with bus matrix (fabric) designs, ETB, NVIC and ARM subsystems. Proficiency in SystemVerilog and UVM Experience with SoC memory sub-system, bus fabric, and DDR interfacing. Experience with standard interfaces such as DMA, PWM, WDOG, Timer etc. Experience with the AMBA- AXI/APB protocols Ability to deal with ambiguity, strong analytical and problem-solving skills. Proactive technical leadership, strong interpersonal skills and communication skills, and a...

[{"Salary":null , "Remote_Job":false , "Posting_Title":"Lead Memory Subsystem Design Verification Engineer (DDR / HBM)" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Proven hands-on experience verifying the digitallogic of DDR/HBM memory subsystems. Solid understanding of JEDEC specifications for LPDDRx/DDRx/HBMx Knowledge of DDR PHY interface (DFI) protocols and specifications. Familiarity with RAS (Reliability, Availability, and Serviceability) featuresin memory subsystems: Requirements Integrate and bring upVerification IPs (VIPs) such as DDR_PHY and memory models into UVMenvironments. Develop drivers, checkers, and scoreboards using SystemVer...

[{"Salary":null , "Remote_Job":false , "Posting_Title":"Lead DSP- SoC Verification Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Specialized in verifying DSP based SoC designs -Knowledge of Smart Cache/TCM -Familiar with Multiply and accumulate unit (MAC) -Understanding of SIMD on vector operation -Knowledge of IEEE fixed and floating points Must be familiar with ARM/RISC-V subsystems. Proficiency in SystemVerilog and UVM Capable of writing C code and working on SystemVerilog-C (SV-C) test-benches. Experience with SoC memory sub-system, LPDDR. Requirements Experience with standard interfaces such as JTAG, SPI, Ethernet, UCIe etc. Experi...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

About The Role Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test ca...

[{"Salary":null , "Remote_Job":false , "Posting_Title":"Principal SoC-GLS Verification Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Collaborate closely witharchitecture and RTL design teams to verify functional correctness of thedesign. Develop detailed test plans and set up test environments accordingly. Assist in building and enhancing verification & GLS flows, automationscripts, and regression infrastructure. Write and implement tests using assembly, C/C++, SystemVerilog based on definedtest plans. Design and implement checkers in SystemVerilog or C-based transactors tovalidate functionality. Write assertions and apply formal verifi...

PMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Computing and Graphics Group, you will help bring to life cutting-edge designs. You will lead a front-end design and integration team, working closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: The ideal candidate will have experience leading a team to develop RTL for SoC subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. KEY RESPONSIBLITIES: Design of IP and subsystems with integration of AMD a...

Understand the design specification , TB architecture Learn in IBM Fusion and Trek verification languages and tools, apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of work experience in IP, Sub-system & SOC level - Exp in creating multiple UVM/SV based env from scratch, Strong in Block Level verification Exp in developing checkers, Scoreboards, Monitors, Test plan development, Code c...

As Logic Lead, you will be responsible for design and development of Compression, Security, and sustainability features for high performance Processors chips. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature Guide and mentor junior engineers. Represent as Design Lead in various forums. Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Estimate the overall effort to dev...

About The Role JD Must have skills. Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to s...

We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team. Key Responsibilities Work closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPs Carry out floor planning, and physically aware synthesis on high-performance IPs Perform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL team Leads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions...

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills VHDL,RTL coding,Mentor DfT tools,Caden...

Skill : DV Lead/Manager Experience : 10 -15Yrs Location : AHMD/BLRE/HYD 10 to 15 years of relevant experience in IP or SOC Verification Must have experience in, developing test bench/test case using System Verilog & UVM Must have experience in functional coverage & assertions development. Experience High Speed Protocol Verification is preferrable Experience in ARM Based SOC Verification Exposure to GLS is an added advantage Experience in PCI/Ethernet/DDR Interested professionals can share your updated profile to chakradhar.marupuru@quest-global.com Current CTC : Expected CTC: Notice Period :

Responsibilities: * Develop RTL designs using Verilog/SystemVerilog * Ensure compliance with MISC industry standards * Collaborate on microarchitecture design projects

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills JTAG,ATPG DRC,LBIST,RTL coding,VHDL,DF...

We are looking for a highly skilled and experienced Lead Engineer to join our team and contribute to the verification of mixes Signal. The ideal candidate should have a deep understanding of the Cadence, AMS along with expertise in system-level development and debugging What You Will Do Proficient in Verilog-AMS, System Verilog, and UVM methodologies Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What You Need to Be Successful Proficient in Verilog-AMS, System Verilog, and UVM methodologies Bonus Points if You Have Experience with Cadence Spectre or similar AMS simulation tools Strong under...

Lead Design Verification: THE ROLE: This is a ASIC Hardware and Firmware Co-Verification Engineering role with the Security IP Team (SECIP). The primary focus of this role is Hardware/Firmware co-verification of various embedded micro-processor subsystems and the associated hardware accelerators in leading edge SOC s. The preferred candidate will also have proven experience in Firmware development and the ability to contribute to Firmware development initiatives. These IP subsystems provide high performance functions to the respective SoC, such as security policy management, cryptography, data compression, high throughput DMA, etc. THE PERSON: You will have strong analytical/problem solving ...

What You ll Be Doing: * Developing emulation solutions large scale designs. * Engaging in software development using C/C++ and synthesizable RTL development with Verilog. * Verifying solutions to ensure high performance and reliability. * Interacting with customers during the deployment and debug phases to ensure smooth implementation. * Collaborating with cross-functional teams to integrate emulation solutions. * Maintaining and enhancing existing emulation solutions to meet evolving industry standards. The Impact You Will Have: * Driving the development of advanced emulation solutions that meet industry standards. * Enhancing the performance and reliability of semiconductor products throug...

Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate shoul...

Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate shoul...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...