Staff Machine Learning Engineer

As a Staff Design Engineer at Lattice, you will play a crucial role in designing and developing RTL for a Machine Learning engine. Your primary responsibility will be to efficiently implement ML operators using resources on low power FPGA. To excel in this role, you must have experience in optimizing data paths for high throughput and low latency. A strong understanding of neural network accelerators and/or DSP processors is essential for success in this position. Key Responsibilities: - Design and develop RTL using Verilog, System Verilog-HDL - Conduct functional simulation using industry standard tools - Implement ML operations such as convolution and BatchNorm - Work on image processing and DSP algorithms - Optimize data models for hardware mapping - Manage FPGA/ASIC synthesis flow and timing closure - Utilize knowledge of computer architecture and memory management - Experience with C and/or SystemC is a plus Qualifications Required: - BE/MTech/PhD in Electronics, Electrical, or Computer Engineering - Minimum of 10 years of experience in RTL design (8 years for MTech, 5 years for PhD) - Independent, self-motivated, and capable of working in dynamic environments - Innovative problem solver with strong communication skills - Desire for cross-team communication and technical documentation If you thrive in a fast-paced, results-oriented environment and wish to contribute to a team-first organization, Lattice offers an opportunity to work with a worldwide community of professionals dedicated to developing cutting-edge programmable logic solutions. Join us and be a part of our energetic team that is focused on R&D, product innovation, and customer service.,