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Staff Engineer Analog Mixed-Signal Verification

Staff Engineer Analog Mixed-Signal Verification

Infineon

3 - 8 years

5 - 10 Lacs

bengaluru

Posted:22 hours ago| Platform:

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Skills Required

semiconductor simulation analog circuit designing soc mixed signal diversity and inclusion vcs uvm silicon validation

Work Mode

Work from Office

Job Type

Full Time

Job Description

Play a key role in the development and implementation of advanced System Verilog real-number modelling methodologies for analog/mixed-signal(AMS) verification, optimizing speed and accuracy trade-offs for pre-silicon validation.
Job Description
In your new role you will: Play a key role in the development and implementation of advanced System Verilog real-number modelling methodologies for analog/mixed-signal(AMS) verification, optimizing speed and accuracy trade-offs for pre-silicon validation.
Collaborate with design and verification teams to define and refine functional verification plans for AMS blocks, ensuring proper integration into complex System-on-Chip (SoC) architectures.
Develop and maintain custom verification frameworks that incorporate mixed-signal and digital simulation environments using industry-leading tools such as Xcelium and VCS.
Create, validate, and deploy behavioral models (VerilogAMS,SystemVerilog ) for AMS components, ensuring compatibility with the digital verification environment and system-level requirements.
Identify bottlenecks in current AMS verification flows and proposeinnovative solutions to enhance efficiency, scalability, and coverage. Provide technical mentorship and training to junior engineers, fostering expertise in AMS verification techniques and best practices Your Profile
You are best equipped for this task if you have:

A degree in Electrical Engineering, Electronics, or related disciplines, with a focus on circuit design or verification.
At least 3 years of professional experience with strong expertise in hardware description languages, particularly System Verilog, including hands-on work in real-number modeling (RNM) and behavioral modelin g of AMS blocks.
Familiarity with VerilogAMS and its application in mixed-signal simulations is a strong plus.
Proficiency with at least one digital simulator, such as Xcelium(Cadence) or VCS (Synopsys). Familiarity with AMS simulationenvironments (e.g., Cadence AMS-Designer) is a strong plus.
Experience in the verification of mixed-signal IC designs, with a clear understanding of integration between analog and digital domains.
Familiarity with EDA tool flows for mixed-signal and digital verification, and knowledge of verification methodologies such as UVM isdesirable.
A problem-solving mindset and the ability to work independently whilecollaborating effectively in a global, cross-functional teamenvironment.
Excellent written and verbal communication skills in English, with an ability to document, implement, and present complex verification methodologies.

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Staff Engineer Analog Mixed-Signal Verification