Principal Engineer, ASIC Development Engineering

Western Digital

2 - 3 years

20 - 25 Lacs

bengaluru

Posted:4 hours ago| Platform:

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Skills Required

asic dft soc verilog test planning perl firmware python physical design embedded software

Work Mode

Work from Office

Job Type

Full Time

Job Description

Define verification strategy, create detailed test plans, and develop robust test benches for SoC verification.
Collaborate with architects, RTL designers, and pre- and post-silicon verification teams to ensure end-to-end verification coverage.
Develop and run UVM/SystemVerilog-based verification environments.
Write, run, and debug C-based tests on SoCs; processor and embedded software knowledge is a must.
Define and achieve functional and code coverage goals; track and close coverage gaps.
Run, debug, and sign off gate-level simulations with SDF annotation.
Develop and validate functional patterns for ATE (Automatic Test Equipment).
Debug complex issues across multiple domains (digital logic, firmware, timing, DFT).
Participate in IP and subsystem-level integration verification and ensure smooth transition to SoC-level verification.
Support low-power verification using UPF and ensure power intent validation.
Automate regression setup, execution, and result analysis using scripting languages (Python, Perl, TCL, etc.).
Contribute to verification methodology improvements, reusable environments, and verification infrastructure scalability.
Work closely with validation and bring-up teams to ensure test portability from pre-silicon to post-silicon.

Qualifications

Required:

BE or MS degree in Electrical Engineering or Computer Engineering, with
9 13 years of experience
.
Deep understanding of
C, SystemVerilog UVM, and coverage-driven verification methodology
.
Proven history of
building and improving SV/UVM-based verification methodology
.

Skills:

Ability to
develop and execute verification plans
at IP, subsystem, and SoC levels.
Knowledge of various interfaces:
PCIe, LPDDR, I C, I3C, SPI, etc.
Proficiency with
C, Verilog, SystemVerilog
, and advanced verification methodologies.
Strong knowledge of
bus protocols
(AXI, AHB, APB) and interconnect fabrics.
Experience in
test plan creation, test development, and test coverage assessment
.
Proficiency in
gate-level simulations
including
SDF annotation and power-aware (UPF/CPF) verification
.
Cross-Functional Collaboration:
Ability to work closely with
design, validation, firmware, and physical design teams
to resolve system-level issues
Performance/Stress Testing:
Familiarity with
performance verification
, traffic generation, and corner-case stress scenarios at SoC level.
Regression Infrastructure:
Experience in
defining, automating, and scaling regressions
in farm environments.
Excellent
debugging and problem-solving skills
with simulation and emulation environments.
Methodology Development:
Proven track record in
building reusable verification environments
, libraries, and methodologies across multiple projects.
Proficiency in
programming/scripting languages
such as Python, Perl, TCL, and Bash.
Strong written and verbal communication skills.
Demonstrated interest in
ASICs, SoCs, storage controllers, flash memory, and semiconductor components
.
Strong
team player
, able to collaborate effectively across architecture, design, and validation teams.

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