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Advanced Micro Devices, Inc
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Sr. SOC level verification -GDP (PCIE,USB,Ethernet ) Engineer

Sr. SOC level verification -GDP (PCIE,USB,Ethernet ) Engineer

Advanced Micro Devices, Inc

5 - 10 years

7 - 12 Lacs

bengaluru

Posted:1 month ago| Platform:

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Skills Required

c++ automation dft coding usb project management ethernet system integration system verilog recruitment

Work Mode

Work from Office

Job Type

Full Time

Job Description

SENIORSILICON DESIGN ENGINEER

THE ROLE (SOC Verification Engineer: GDP DV ):

Work on SOC level verification activities for GDP (PCIE , USB , Ethernet , I2C , I3C , Uart , SPI) and subsystem or signature IP s in the complex SOC. He will be responsible for verifying and integration.
Add on responsibility SOC Integration after having co-ordination with IPs, SOC (Design, DFT & PD) teams. To take complete IP integration responsibility, including the deployment verification.
Understand spec, interact with customer, team members, lead and come up with testplan, code testcases, checkers, UVM agents, scoreboards and assertions.

THE PERSON:

Engineer with strong self-driving ability.
Need excellent communication skills (both written and oral)
Strong problem-solving skills, go to person for UVM coding, Testcase coding, checkers and assertions.

KEY RESPONSIBILITIES:

Understanding Ips like (PCIE , USB , Ethernet , I2C , I3C , UART , SPI)
IP deployment to complex SOCs and get the integration testing done.
Testcase coding, Debugging issues, regressions, UVM agent coding, checkers coding, scoreboard coding and Assertions coding.

PREFERRED EXPERIENCE:

Knowledge of High speed peripheral (PCIE,USB,Ethernet) and Low speed peripherals (I2C,I3C,UART,SPI)
Expertise in IP, Subsystem and SOC Verification with specialization in Integration, verification tools
Strong hands-on experience in different SOC Verification activities, UVM, System Verilog, kv, X86, C++, HW/SW co-verification, Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc.
Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc.
Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence.
JIRA based project management is a plus.

ACADEMIC CREDENTIALS:

BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE
~5-10 years of strong DV experience in IP, Sub System & SOC Verification, IP deployment/integration.

#LI-SR4

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