SMTS/Principal FPGA Design Engineer

As a member of our team at MarvyLogic, you will be part of a culture that values passion for technology solutions and individual growth. We believe in fostering an environment where your contributions make a tangible impact on businesses and provide opportunities for personal development. **Key Responsibilities:** - Utilize your minimum of 10 years of experience in FPGA Design and Debug, with a preference for working with Xilinx Ultrascale+ and Virtex7 - Demonstrate proficiency in tools like Xilinx Vivado/Coregen/Synplify and develop/maintain Timing/IO constraints (UCF) - Manage multiple high-speed clock domains, integrate third-party IP onto Xilinx transceivers, and work on FMC daughter-cards, High-Speed Cables/Connectors, etc. - Utilize extensive debugging experience using Xilinx ILA, Protocol Analyzers, Oscilloscope, Logic Analyzers, etc. - Employ PERL/TCL scripting and database management for FPGA and ASIC RTL communication - Apply knowledge of front-end RTL tools for RTL Simulation, Synthesis, DFT, Timing - Modify/adapt RTL designs for FPGA implementation, optimize designs for FPGA area/performance goals, and collaborate with DV and Firmware/Software teams throughout the validation process **Qualifications Required:** - A minimum of 10 years of experience in FPGA Design and Debug, preferably working with Xilinx Ultrascale+ and Virtex7 - Proficiency in utilizing tools such as Xilinx Vivado/Coregen/Synplify and developing/maintaining Timing/IO constraints (UCF) - Experience with managing multiple high-speed clock domains and integrating third-party IP onto Xilinx transceivers - Familiarity with working on FMC daughter-cards, High-Speed Cables/Connectors, etc. - Extensive debugging experience using Xilinx ILA, Protocol Analyzers, Oscilloscope, Logic Analyzers, etc. - Proficiency in PERL/TCL scripting and database management between FPGA and ASIC RTL - Knowledge of front-end RTL tools such as RTL Simulation, Synthesis, DFT, Timing If you possess the specified qualifications and are eager to take on the responsibilities of effectively collaborating with multi-site teams and overseeing FPGA netlist releases and ASIC product life cycle stages, we encourage you to apply for this challenging and rewarding opportunity at MarvyLogic.,