Senior Engineer Digital Functional Verification

In your new role you will:

• create and define verification plans;
• develop verification environments for our ICs using UniversalVerification Methodology (UVM).
• draw on test scenarios using SystemVerilog;
• verify functionality using the Constrained Random approach;
• develop assertions in SystemVerilog for formal verification;
• Interact with other disciplines, such as Concept and ApplicationEngineering, to define verification plans and strategies;
• provide proactive support to users of our verification flowenvironment;
• be responsible for our verification methods;
  

Your Profile

You are best equipped for this task if you have:

• You have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline;
• You have at least 3 years of experience in Constrained-Random Metric-Driven Verification
• You have capabilities and experience in working with microcontroller-based ICs, as well as security and safety requirements;
• You have good know-how with UVM especially using SystemVerilog.
• Have knowledge of firmware and RTL design (VHDL);
• Ideally have knowledge of working with Verification IPs (VIPs)
  

Contact:

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