Senior Design Verification Engineer (ASIC/SoC)

10 years

0 Lacs

Posted:1 month ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

Job Title: Senior Design Verification EngineerExperience: 4 – 10 yearsLocation:

Siruseri, Chennai (Work from Office only)

Industry: Semiconductor / VLSI

Role Summary

We are looking for experienced

Design Verification Engineers

who have built

UVM-

based testbenches from scratch and contributed to multiple successful tapeouts.Candidates should have deep expertise in

functional verification using SystemVerilog

and

UVM

and be comfortable owning verification deliverables end-to-end.

Required Skills

 Strong hands-on experience with

SystemVerilog and UVM

methodology. Solid knowledge of

SoC/ASIC

architecture and verification lifecycle. Hands-on experience in

writing testbenches

, stimulus, checkers, monitors, andscoreboards . Strong debugging skills using simulation tools like

VCS, Questa.

 Experience with functional and code coverage. Familiarity with

Register Abstraction Layer (RAL)

modeling and verification. Excellent analytical and problem-solving skills. Strong communication and teamwork abilities.

Candidate Requirements

 Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related fields. Experience:

4–10 years of relevant experience in ASIC/SoC design verification.

 Must have contributed to

at least three or more successful tapeouts.

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