91 Scan Insertion Jobs - Page 4

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

We are hiring DFT Engineer | Hyderabad Notice Period: 30 Days Position: DFT Engineer Looking for passionate professionals with 4 to 6 years of experience in Design for Test (DFT) to join our growing team in Hyderabad ! Key Responsibilities: Drive innovative DFT implementation at RTL and Gate level for SoC designs at both hard macro and chip top level, including: Scan insertion MBIST (Memory BIST) LBIST (Logic BIST) Boundary Scan Generate and validate ATPG patterns through simulation DFT verification using RTL and Gate-level simulations Collaborate with cross-functional teams across: Static Timing Analysis (STA) Synthesis Logic Equivalence Check (LEC) CLP Functional Verification & Validation Tool Proficiency: Experience with DFT tools from: Siemens Synopsys Cadence Technical Skills: Strong coding skills in: Verilog, VHDL C/C++ TCL, Perl, Python

Dear Candidates, Greetings!! We are hiring for one of the Globalized Semiconductor Manufacturing MNC that specializes into Design Verification , Embedded software, Analog Layout, Analog Design, RTL Design, Design for test Job Type: FTE Job Role:- DFT Engineer Experience: 8+ Years Location: Bangalore Work Mode: Hybrid Notice Period: Serving to 45 days Budget: As Per Market Standards Mandatory Skills: Good understanding on DFT concepts like SCAN/ATPG/BSCAN/MBIST. Experience in Mbist insertion using tessent and mbist validation Experience in ATPG, drc fix and coverage analysis. Experience in scan synthesis. Hands on experience on Simulations with and without timing. Post silicon debug support. Interested candidates can share their updated resume on Gurpreet@selectiveglobalsearch.com

Position: DFT Lead Engineer ( Cluster porject with 7-8 Junior team) Location: Bangalore, India Experience: 8+ years in ASIC/SoC DFT About the Role We are seeking an experienced Design-for-Test (DFT) Lead Engineer to drive test architecture, strategy, and execution for advanced AI-centric SoCs. This role demands deep technical expertise, leadership skills, and the ability to collaborate closely with cross-functional design teams to ensure high-quality, production-ready silicon. Key Responsibilities Define and own the DFT architecture for complex AI/ML SoCs, including scan, MBIST, LBIST, JTAG, and boundary scan strategies. Drive ATPG, fault modeling, pattern generation, and compression flow for optimal coverage. Collaborate with RTL, physical design, and verification teams to ensure seamless DFT integration. Lead silicon bring-up and production test correlation efforts. Work with test engineering teams to optimize test time and yield. Provide technical guidance, mentoring, and review of junior engineers work. Interface with EDA vendors to evaluate tools, flows, and methodologies for DFT improvements. Required Skills & Experience 8+ years of hands-on DFT design and implementation for large SoCs. Strong experience in scan insertion, ATPG, MBIST/LBIST, boundary scan, and IJTAG . Proficiency in EDA tools such as Synopsys DFTMAX/TetraMAX , Cadence Modus, or equivalent. Solid understanding of ASIC design flow , timing closure, and physical design constraints. Experience in silicon bring-up and production test environments. Excellent leadership, problem-solving, and communication skills. Preferred Qualifications Experience with AI, high-performance computing, or data-center class chips . Knowledge of advanced process nodes (5nm/7nm). Exposure to yield analysis and debug methodologies. Why Join Us? Work on cutting-edge AI processors that are redefining performance, efficiency, and scalability in the next generation of computing. Join a team where innovation meets execution, and your contributions directly shape silicon success.

Required Technical and Professional Expertise in DFT Minimum 6 to 8 years of relevant experience . Proficient in DFT architectures & methodologies that includes Scan insertions, ATPG, MBIST, JTAG, etc. Sound knowledge of DFT tools/methodology from cadence /Synopsys/Mentor tools Good Experience in Python/Perl/TCL scripting

Block & Soc level DFT insertion. Scan insertion & DRC cleanup. ATPG, Pattern generation for Stuck-At, at-speed test, iddq, path delay, fault grading. Coverage debug. Memory testing, MBIST Pattern generation.

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team, you will be required but not restricted to insertion, pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Hands-on experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in Asics/processor flow and post silicon validation

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team, you will be required but not restricted to insertion, pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Hands-on experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in Asics/processor flow and post silicon validation

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s microprocessor chip design team. As a member of DFT team, you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with Gate-Level DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in processor flow and post silicon validation

Job Description: We are hiring a Design-for-Test (DFT) Engineer to work on cutting-edge SoC and FPGA designs. The ideal candidate should have a solid background in digital design and hands-on experience with industry-standard DFT tools and fault models. Responsibilities: • Collaborate with design teams to integrate and validate DFT structures across IP and SoC levels. • Implement Scan Compression techniques and develop test strategies for stuck-at, transition, and delay faults. • Use tools such as TestKompress and Tessent for pattern generation, MBIST, and fault diagnosis. • Perform scan retargeting and assist in silicon debug for scan and MBIST failures. • Support post-silicon yield improvement and diagnosis during product ramp. • Work on RTL-based test logic insertion and verification using Verilog/VHDL. • Scripting knowledge in Perl or Shell is a plus; familiarity with FPGA environments is an advantage.

Preferred candidate profile DFT Fundamentals including JTAG, Scan, ATPG, IEEE 1687 iJTAG, EDT Architecture Scan Insertion using Fusion Compiler or other EDA tools ATPG Coverage Analysis and DRC clean up ATPG patterns simulation and debug using SNPS VCS and Verdi tools Understanding of Design for Test methodologies and DFT experience (e.g. JTAG 1149.x, IEEE 1500, IEEE 1687 iJTAG, Scan, ATPG, Memory BIST, etc.) Familiar with DFT flow and EDA tools, including Fusion Compiler, Synopsys Tmax or Mentor Testkompress/Tessent, etc. Experienced with Verilog, System Verilog, VCS simulation tool, Perl/Shell scripting, and Verilog RTL design Experience in debugging Compressed ATPG patterns, MBIST, and JTAG/1500 related issues Experience in test failures debug to determine the root cause; work with design engineers to resolve design defects and correct any test issues Experience with STA constraints development, analysis for DFT modes and SDF simulations Good communication skills

Role & responsibilities • Hands-on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis Proficiency in simulation debug with timing/SDF Experience with LBIST and Mixed Signal Radar ICs is highly desirable Ability to debug and root cause simulation failures Must be proactive, collaborative, and detail-oriented, capable of exercising independent judgment Preferred candidate profile Immediate joining

We are looking for a highly experienced DFT Lead Engineer to take ownership of Design-for-Test (DFT) architecture, implementation, and sign-off for complex flat SoC designs. This role requires deep expertise in PNR (Place-and-Route) within Cadence flow. Key Responsibilities Lead DFT strategy and implementation for flat SoC designs from RTL through tape-out. Develop and integrate test architectures including scan insertion, MBIST, LBIST, JTAG, and boundary scan. Work closely with the PNR team to ensure DFT structures are timing- and placement-aware. Drive test mode constraint creation and ensure compatibility with functional modes. Perform gate-level simulations for test logic verification. Own ATPG pattern generation and coverage analysis for manufacturing test. Lead reviews and mentor junior DFT engineers in best practices. Qualifications Must-Have: Bachelor s or Master s degree in Electrical/Electronics/Computer Engineering or related field. 10 12 years of hands-on DFT experience in ASIC/SoC projects. Proven PNR experience to handle flat SoC designs in Cadence flow Strong knowledge of scan insertion, MBIST, LBIST, boundary scan, JTAG, and related standards (IEEE 1149.x). Experience with Synopsys DFT Compiler, Tessent, or equivalent DFT tools. Good understanding of STA and SDC constraints for test modes. Familiarity with ECO flows in post-PNR stages for DFT fixes. Nice-to-Have: Automotive semiconductor industry experience Proficiency in scripting ( Tcl, Perl, Python ) for automation. Low-power DFT experience with UPF/CPF. Exposure to signal integrity considerations for test structures. Prior technical leadership or mentoring experience.