91 Scan Insertion Jobs - Page 2

Required Technical and Professional Expertise in DFT Minimum 9 to 13 years of relevant experience . Proficient in DFT architectures & methodologies that includes Scan insertions, ATPG, MBIST, JTAG, etc. Sound knowledge of DFT tools/methodology from cadence /Synopsys/Mentor tools Good Experience in Python/Perl/TCL scripting

Key Responsibilities: Ownership of Scan/ATPG and MBIST flows for complex SoCs Expertise in Synopsys tools , especially SMS (Synopsys Memory Solution) Deep understanding of MBIST architecture and memory repair techniques Hands-on experience with Scan insertion and ATPG for large devices using hierarchical DFT flows Debug and support issues during DFT implementation and silicon bring-up Collaborate closely with RTL, PD, and test engineering teams

ASIC DFT Engineering Technical Leader :: Design for testability, JTAG, Scan and BIST :: Exp 8+ yearsDFT Engineering Technical Lead Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Prior experience working with Gate level simulation, debugging with VCS and other simulators. Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Prior experience with Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis Past experience with Post silicon validation using DFT patterns.

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 7+ years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Prior experience working with Gate level simulation, debugging with VCS and other simulators. Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Prior experience with Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis Past experience with Post silicon validation using DFT patterns.

DFT Design Engineer (6 to 15 Years) DFT Engineer Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore] Experience: 4 to 15 Years Openings: 3 Positions Preferred - Immediate to 90 Days (Notice Period) About the company: ACL Digital, an ALTEN Group Company, is a digital product innovation and engineering leader. We help our clients design and build innovative products (AI, Cloud, and Mobile ready), content and commerce-driven platforms, and connected, converged digital experiences for the modern world through a design-led Digital Transformation framework. By integrating our strategic design, engineering, and industry capabilities, we help our clients decode the digital world and accelerate their growth journey. Headquartered in Silicon Valley, ACL Digital is a leader in design-led digital experience, innovation, enterprise modernization, and product engineering services converging to Technology, Media & Telecom. We are a talented workforce and part of the 50,000+ employee ALTEN Group, spread across more than 30 countries, offering a multicultural workplace and a collaborative knowledge environment. Job Description: 6+ years of hands-on experience in DFT methodologies. Proficiency with DFT tools (e.g., Synopsys DFT Compiler, Mentor Tessent, Cadence Modus). Strong understanding of test methodologies including scan insertion, boundary scan, BIST, and memory testing. Familiarity with RTL design and verification processes (Verilog/VHDL, UVM, System Verilog). Hands-on experience in automatic test pattern generation (ATPG) and fault simulation. Strong debugging and troubleshooting skills in both simulation and silicon environments. Excellent analytical skills with the ability to analyze large sets of test data and recommend improvements. Experience with JTAG/IEEE 1149.x boundary scan standards.

Role & responsibilities Excellent understanding of DFT architectures & methodologies which includes Scan insertion, ATPG, JTAG, SIMS etc. Must have experience in generating scan patterns and coverage statistics for various fault models like stuck at, Transition faults and path delay. Experience in Scan Stuck-At and At-Speed coverage exploration, simulation and debug. Hands on experience in state-of-the-art EDA tools for DFT, design and verification. STA for DFT mode timing constraint development and exploration is a plus. Excellent debug skills and demonstrated experiences in Perl /TCL/Python scripting is a plus. Good Communications skills and the ability to effectively work with cross functional teams across geographies are required. Design experience in MBIST, LBIST and Analog DFT is an added advantage.

Job Description The person is responsible for ensuring the integrity of a design by analyzing signal connectivity, specifically related to Design for Testability (DFT) features, utilizing Spyglass tools to identify and report potential violations within the test logic. Expertise should include and not limited to the following Strong understanding of digital circuit design principles and timing analysis concepts Experience with RTL design, synthesis Proficiency in scripting languages like TCL, Perl, or Python for automation Excellent problem-solving and debugging skills Strong communication and teamwork abilities to collaborate with cross-functional teams

What are the responsibilities in this role? Develop and execute pre-silicon verification test plans for DFT features of the chip. Develop directed and random verification tests to validate the functionality. Verify DFT design blocks and subsystems (such as MBIST, high speed IO PHY, fuse, clocks, reset) using complex SV or C++ verification environments. Construct SystemVerilog and/or C/C++ models and test sequence libraries for simulation. Build test bench components including agents, monitors, scoreboards for DUT. Compose tests, assertions, checkers, validation vectors and coverage bins to ensure verification completeness. Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives. Develop high coverage and cost effective test patterns, and take part in ATE bring-up. Post silicon ATE and System level debug support of the test patterns delivered. Optimize the test patterns to improve the test quality and reduce test costs. What is the experience and knowledge you should have? 3 to 6 year experience in DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing) Strong background in Verilog, SystemVerilog (SV), SVA, UVM verification methodologies and C++ Strong debug skills and experience with debug tools such as Verdi. Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi Experience with scripting languages like Tcl/Perl/Ruby/Python Working knowledge of Unix/Linux OS, file version control. Additional skills: Experience in ATE debug, Synthesis, formal/LEC, or power analysis will be a plus. Strong analytical/problem solving skills and pronounced attention to details Knowledge of STA Constraints for various DFT modes. Excellent written and verbal communication

Role & responsibilities Leading DFT ATPG implementation, integration and verification of System-on-Chip (SoC) from initial specification till tapeout and production. Ensure Test Coverage Goals are met at SoC Level. Addressing test quality targets in DFT architecture and test pattern generation. Leading various aspects of Test architecture including MBIST, Scan & ATPG. Work with different functions like front-end design, verification and physical design to ensure production quality silicon. Specific Knowledge/Skills Master/Bachelors Degree in Electrical/Electronic Engineering. Experience of 6 to 10 Years in DFT with successful delivery of production quality chips. Senior SoC DFT engineers, with experiences in all aspects of DFT, including MBIST, scan & ATPG, logic BIST. Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design. Self-motivated. Excellent written and verbal communication skill. Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components. Should be a team player and willing to work with cross functional teams in issues resolution.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years’ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Sr DFT Engineers and Managers - location remote any where in India Job Summary Our clients Arasan Chip Systems (www.arasan.com) based in US are seeking for their India Development Center Senior and Experienced DFT Engineer with 68 years of hands-on expertise in Design-for-Test methodologies and implementation for complex SoC designs. The candidate will be responsible for developing and integrating DFT architectures, driving ATPG and MBIST flows, and working closely with RTL design, physical design, and test teams to ensure high test coverage and silicon readiness. Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan (JTAG), and test points. Develop and run ATPG and MBIST for various memory instances. Generate and validate test patterns (stuck-at, transition, path delay). Collaborate with RTL, synthesis, and physical design teams to ensure DFT integration and timing closure. Participate in silicon bring-up and ATE support. Support internal reviews, audits, and DFT documentation. Skills Strong experience with industry-standard DFT tools (Mentor Tessent, Synopsys DFTMAX, Cadence Modus, etc.). Hands-on experience in scan insertion, ATPG, MBIST, boundary scan, and test compression techniques. Familiarity with ATE pattern generation and silicon debug flows. Solid understanding of RTL/gate-level simulation, synthesis, STA, and timing-aware DFT flows. Proficiency in scripting languages (TCL, Perl, Python) for automation. Excellent analytical and problem-solving skills. Qualifications B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related field. 6–8 years of relevant experience in DFT for ASIC/SoC design. Preferred Exposure to low-power DFT methodologies (UPF/CPF flows). Prior experience with automotive or high-speed PHY IP integration is a plus. Knowledge of IEEE standards (1149.1, 1500, 1687).

Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan (JTAG), and test points. Develop and run ATPG and MBIST for various memory instances. Health insurance

Role & responsibilities Leading DFT ATPG implementation, integration and verification of System-on-Chip (SoC) from initial specification till tapeout and production. Ensure Test Coverage Goals are met at SoC Level. Addressing test quality targets in DFT architecture and test pattern generation. Leading various aspects of Test architecture including MBIST, Scan & ATPG. Work with different functions like front-end design, verification and physical design to ensure production quality silicon. Specific Knowledge/Skills Master/Bachelors Degree in Electrical/Electronic Engineering. Experience of 6 to 10 Years in DFT with successful delivery of production quality chips. Senior SoC DFT engineers, with experiences in all aspects of DFT, including MBIST, scan & ATPG, logic BIST. Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design. Self-motivated. Excellent written and verbal communication skill. Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components. Should be a team player and willing to work with cross functional teams in issues resolution. Preferred candidate profile Perks and benefits

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Job Description: Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.

Experience in dft scan insertion, atpg at ip and soc level Hands on experience in atpg timing and no-timing simulations Proficient in doing basic unit-level verification using simulations. Scan/atpg patterns & test flows development, debug, test and characterization

As a member of DFT team , you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation. Proven expertise in analysing and resolving DRCs/TSVs . Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues. Hands-on experience with DFT verification, both with and without timing annotations. Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery . Hands on experience on industry standard tools used for DFT features. Proficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks. Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs. Excellent analytical and problem-solving skills, with a keen attention to detail. Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Preferred technical and professional experience Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design Experience working with ATE engineers for silicon bring up, silicon debug and validation. Experience in processor flow and post silicon validation

Hi All, We have immediate hiring for DFT Engineers for HYD Location. Exp - 5+ yrs Location - HYD NP - immediate to 15 days max JD - DFT, DFT Architecture, ATPG Interested candidates, Kindly me your profile to anand.arumugam@modernchipsolutions.com

Job Title : DFT Engineer Location : Bangalore, India Experience : 4 to 8 Years Role Overview We are looking for a passionate and detail-oriented Design-for-Test (DFT) Engineer to join our dynamic ASIC design team. As a DFT Engineer, you will be responsible for architecting and implementing robust test strategies to ensure first-pass silicon success in complex SoC designs. Key Responsibilities Develop and implement DFT architecture and methodologies for SoC/ASIC designs Design and insertion of scan chains , MBIST , LBIST , and boundary scan (JTAG) Work closely with RTL, STA, and Physical Design teams to integrate and validate DFT logic Generate and validate test patterns (ATPG/MBIST) and support silicon bring-up and validation Ensure DFT logic meets coverage goals , timing, and area/power constraints Work with ATE teams on test vectors and debug silicon issues Required Skills & Qualifications 4-8 years of experience in DFT implementation and verification Hands-on experience with tools like Mentor Tessent, Synopsys DFT Compiler, TestMax, TetraMAX Strong knowledge of scan insertion , ATPG , JTAG (IEEE 1149.x) , MBIST , and LBIST Good understanding of ASIC/SoC design flow , RTL to GDSII Proficiency in scripting (TCL, Perl, or Python) for automation Experience working with advanced technology nodes (16nm, 7nm or below) is a plus Excellent analytical, problem-solving, and communication skills Nice to Have Experience in DFT signoff and silicon debug Knowledge of safety-critical designs (ISO 26262) or low-power DFT techniques Familiarity with ATE patterns and post-silicon validation Why Join Us? Work on industry-leading SoCs and IPs Collaborate with some of the best minds in the semiconductor industry Fast-paced, innovation-driven, and engineer-friendly environment Flexible work culture and competitive benefits

Job Descriptions for DFT: Required Technical and Professional Expertise in DFT Minimum 6 to12 years of relevant experience . Proficient in DFT architectures & methodologies that includes MBIST insertion, pattern generation etc. Sound knowledge of DFT tools/methodology from cadence /Synopsys/Mentor tools Good Experience in Python/Perl/TCL scripting Job Location : Bangalore Job Descriptions for DFT: Required Technical and Professional Expertise in DFT Minimum 9 to 13 years of relevant experience . Proficient in DFT architectures & methodologies that includes Scan insertions, ATPG, MBIST, JTAG, etc. Sound knowledge of DFT tools/methodology from cadence /Synopsys/Mentor tools Good Experience in Python/Perl/TCL scripting Job Location : Bangalore

Roles and Responsibility 5 years to 15 yrsdesign experience. Experience withowning chip level DFT and Post Silicon debug / analysis. Understanding of DFTarchitectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISRetc.), scan chain insertion and verification. Must have experiencegenerating scan patterns and coverage statistics for various fault models likestuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, patterngeneration for Memories(E-fuse etc.). Experience debugging tester failures ofscan patterns, diagnosis and pattern re-generation. Understandinggeneration of functional patterns for ATE Knowledge of atleast any one of an industry standard DFT tools (Cadence Modus, SynopsysTetramax, Mentor Tessent Tools, etc) Design experience inMBIST / LBIST is an added advantage. Good understandingof constraints development for Physical Design Implementation / Static TimingAnalysis. Responsibilities: Must have experience generating scan patterns andcoverage statistics for various fault models like stuck at(Nominal and VBOX),IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E- fuseetc.). Experience debugging tester failures of scan patterns, diagnosis andpattern re-generation. Understanding generation of functional patterns forATE Knowledge of at least any one of an industrystandard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools,etc) Design experience in MBIST / LBIST is an addedadvantage. Good understanding of constraints development forPhysical Design Implementation / Static Timing Analysis. Desired Skills: Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits andit s design cycles is an added advantage. Effective communication skills to interact with allstakeholders. Team and People Skills: The candidate should havegood people skills to work closely with the systems, analog, layout and testteam Must be highly focused and remain committed toobtaining closure on project goals Role: DFT Engineer Department: Design For Test & Debug Employment Type: Full Time, Permanent

Responsibilities: * Ensure compliance with industry standards and customer requirements. * Design DFT solutions using ATPG, MBIST, Scan Insertion, JTAG tools.

Position: DFT Engineer (ASIC) Experience: 2+ Years Location: Hyderabad Job Summary: We are seeking a talented DFT (Design for Testability) Engineer with expertise in ASIC design and a strong background in EDA tools such as Synopsys . The ideal candidate will have hands-on experience in developing, implementing, and optimizing DFT architectures to ensure high test coverage and manufacturability. Key Responsibilities: Design and implement DFT methodologies for ASIC projects, including scan insertion, ATPG, and BIST. Work with EDA tools from Synopsys (such as TetraMAX, DFT Compiler, TestMAX, etc.) to achieve high test coverage and efficient test solutions. Develop and validate test strategies for scan-based testing, MBIST, and boundary scan. Collaborate with RTL and physical design teams to ensure seamless DFT integration. Perform fault simulations , analyze test results, and drive improvements in test efficiency. Optimize DFT architectures for low-power, high-performance, and manufacturability . Support silicon bring-up and debug of test patterns on actual hardware. Work closely with foundries and test teams to ensure smooth production testing. Keep up to date with the latest DFT methodologies, trends, and innovations. Required Skills & Qualifications: 4+ years of experience in DFT implementation for ASIC designs. Proficiency in Synopsys EDA tools for test implementation and validation. Solid understanding of digital design, scan insertion, ATPG, and BIST . Experience with fault modeling, test coverage analysis, and debugging . Strong scripting skills in Python, Perl, or TCL for automation. Ability to work in a multi-disciplinary team and communicate technical concepts effectively. Preferred Qualifications: Experience with Post-Silicon Debug and ATE Testing . Knowledge of Verilog/VHDL and simulation tools . Familiarity with industry-standard DFT flows and methodologies .

Like Requirements: 5 to 10 years of hands-on experience in DFT methodologies , with expertise in Scan & ATPG, MBIST Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence. Experience in fault modeling, pattern generation, and coverage analysis . Proficiency in scripting (TCL, Python, Perl, or Shell) for automation. Excellent problem-solving skills and ability to work in a fast-paced environment. Job Responsibilities: Implement and validate DFT architectures for complex SoCs. Perform scan insertion and ensure proper integration into the design. Develop and optimize ATPG patterns to achieve high fault coverage. Work closely with RTL, verification, and physical design teams to resolve DFT-related issues. Support post-silicon bring-up, debug, and ATE (Automated Test Equipment) testing.

Roles and Responsibilities Develop RTL code using Verilog/VHDL Work with Mentor DfT tools and Cadence tools for design and verification Perform scan insertion, JTAG, ATPG DRC, and coverage analysis Debug simulations using timing and SDF Contribute to LBIST and Mixed Signal Radar IC-related projects (preferred) Investigate simulation failures and perform root cause analysis Collaborate with cross-functional teams; work independently and proactively Communicate effectively with both written and verbal communication