Rtl Verification Engineer

0 - 3 years

1 - 2 Lacs

Posted:2 weeks ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

RTL Verification Engineer

Job Title:

Responsibilities:

  • Develop testbenches in System Verilog
  • Write and execute testcases for RTL validation
  • Perform code coverage and functional coverage analysis
  • Debug simulation failures and regressions

Requirements:

  • Good knowledge of Verilog/System Verilog
  • Basic understanding of UVM and testbench architecture
  • Experience with simulation tools like VCS or Questa

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