RTL Engineer

Role 1: Sr. RTL Synthesis Engineer

Parent company : TEKsystems

Client/ Domain:

Notice Period Expectations : Immediate to 45 days

Work Location (client): Hitec city, Hyderabad

Work timings: Normal Working hours

Qualification :Bachelors Degree / MS or equivalent work experience in Electrical Engineering or similar technology area.

Experience : 3+ Years

Skills required

1.RTL Coding (Verilog/ Sys Verilog) at least intermediate Proficiency

2.Solving timing Constraints and STA.

3.Proficiency in Digital Electronics Design concepts

4.Proficiency in FPGA design flow and vivado.

5.Previous Exposure to AMD Products is an Added advantage

Basic Job Deliverable | RTL synthesis

several Vivado product areas, such as design entry, synthesis, implementation, and help engineering address them effectively

emphasis on timing closure and compile time, as well as productivity with the new Versal ACAP family.

Functional Skills

3.Develop and deliver training materials on new features and methodologies.

Stay current with and propose the internal use of industry approaches, algorithms, and practices.

Interview Process ( 2 Levels)

1.Technical round (panel of 3 , Areas covered Verilog/Sys Verilog, Digital Design, Timing Constraints/analysis, STA, FPGA Flow.

2.Techno managerial , Understanding Role fitment and exploring possible areas you could contribute to team

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Role 2 : RTL FPGA Engineer

Parent company : TEKsystems

Client/ Domain:

Work Location (client): Hitec city , Hyderabad

Work timings: Normal Working hours

Qualification

Experience Level

Required skill for the Job | RTL FPGA Engineer

-New IP Design or existing IP Design role,

RTL Coding IP Design/ Verification/ integration

Timing analysis, STA along with tools like Vivado

-Experience on FPGA platforms like AMD(XILINX)/Altera.

digital hardware designing

-Experience in scripting language like perl, python and tcl

-Working experience on Linux.

-Ensure to complete design and timing verification tasks within allotted timelines.

-Ability to work individually and in a team.

Basic Job Deliverable:

1.Design, implementation, test, integration, and delivery of system level digital designs for FPGA blocks timing verification

2.Perform task of debugging design timing related issues on different FPGA families

3.Perform the work of manifold segmentation of the FPGA designs.

4.Run internal scripts for performance testing and update scripts when necessary

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Did you know About TEKsystems?

Allegis Group

• The 6th Largest staffing company in the world and the 2nd Largest in the US,One of the top vendors to 90% of Fortune 500 companies.

• Every year we help our clients hire over 80,000 induviduals across different parts of the world.

• In India, TEKsystems currently has 4000+ employees at various Fortune 500 companies across the country and have wide Operations in North America, Europe and Asia with over 300 offices across locations.

• For the second consecutive year, TEKsystems was named to Fortune magazine’s “100 Best Companies to Work For” in 2014.

• Please visit - www.teksystems.com ; www.allegisgroup.com, for more information.