RTL Design Engineer

TekPillar®

5 years

0 Lacs

noida uttar pradesh india

Posted:1 day ago| Platform:

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Skills Required

design verilog xilinx synthesis simulation interface software engineering vivado architecture flow timing signal

Work Mode

On-site

Job Type

Full Time

Job Description

Position:

Experience:

Location:

RTL Design Engineer

Key Responsibilities

Design, develop, and verify
FPGA modules
using Verilog
Work with
Xilinx Vivado
for synthesis, simulation & implementation
Develop solutions on
Xilinx Zynq UltraScale+
platforms
Interface and integrate peripherals:
I2C, SPI, DDR, eMMC, AMBA, PL/PS
Collaborate with hardware, software & system engineering teams for complete design delivery

Required Skills & Qualifications

5+ years of strong hands-on experience in
Verilog
Bachelor’s or Master’s degree in
Electronics / Computer Engineering
Expertise in
Xilinx Vivado Design Suite
Strong understanding of
FPGA architecture, synthesis flow & timing closure
Hands-on experience with
Xilinx Zynq UltraScale+
family
Experience with interface protocols:
I2C, SPI, DDR, eMMC, AMBA

Nice to Have

Experience in
high-speed signal design
Knowledge of
HDMI interface

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