Principal Physical Design Engineer

Analog Devices

10 - 15 years

20 - 25 Lacs

bengaluru

Posted:1 day ago| Platform:

Apply

Skills Required

physical design static timing analysis cad innovus floorplan drc debugging perl tcl ppa digital synthesis asic sta python eda finfet netlist lvs ir rtl analysis cadence physical verification sta tools node dft timing closure synopsys vlsi eda tools

Work Mode

Work from Office

Job Type

Full Time

Job Description

Lead and perform all major steps of the digital physical design flow, including block-level and top-level floorplanning, placement, clock tree synthesis, routing, and timing closure.
Collaborate directly with RTL and synthesis teams for timing constraint setup, synthesis refinement, and netlist quality.
Develop and implement strategies for power integrity, IR-drop analysis, EM verification and low-power physical design using UPF/CPF methodologies.
Hands-on execution of physical verification: DRC, LVS, ERC, antenna checks, reliability and manufacturability checks, and ECO implementations.
Drive timing analysis and closure at all implementation stages, using static timing analysis (STA) and advanced node-specific signoff flows.
Own integration of hard macros, blocks, and IP; define and optimize power grid, pad ring, and custom routing as required.
Propose and develop automation for various physical design flows using TCL, Python, or other scripting languages for process improvement.
Perform design partitioning, floorplan, and chip assembly for hierarchical and complex designs targeting advanced process nodes ( 7nm).
Interface with DFT, signal/power integrity, package, and test teams to ensure comprehensive signoff and manufacturability.
Actively contribute to methodology improvements, flow development, and CAD tool evaluations.
Participate in engineering and peer reviews, providing direct, hands-on technical guidance to the team.

Required Qualifications

Bachelor s or Master s in Electrical/Electronics/VLSI Engineering or a related discipline.
10+ years hands-on experience in all aspects of digital physical design for ASIC/SoC development; experience with advanced FinFET nodes is a plus.
Expert knowledge of EDA tools for physical design: Cadence Innovus, Synopsys ICC2, Mentor Olympus, STA tools.
Deep technical expertise in timing closure, PPA optimization, physical verification, and IR-drop/EM checks.
Scripting skills in TCL, Python, or Perl for workflow automation and data analysis.
Proven track record of successful tapeouts (block and full chip) at advanced nodes, including hierarchical and top-level physical implementation.
Experience with low-power design techniques and physical implementation of complex multi-power/voltage domain chips.
Strong debug and analytical skills, including post-route timing, layout closure, and design ECO execution.
Excellent ability to document flows and report findings.

Nice-to-Have Skills

Hands-on experience integrating mixed-signal or analog blocks, custom IPs and hard macros.
Familiarity with DFT insertion, boundary scan, scan chain stitching at physical level.
Involvement in physical design methodology development and CAD flow automation.
Publications or patents in physical implementation, EDA flow innovations, or advanced process optimizations.

More Jobs at Analog Devices

Engineer, Digital Design Engineering

Bengaluru

Experience: Not specified

INR 2 - 6 Lacs

Software Full Stack Engineer, Software Development Engineering

Bengaluru

2 - 4 yrs

INR 4 - 6 Lacs

Engineer, Digital Design Engineering

Bengaluru

1 - 6 yrs

INR 3 - 8 Lacs

Project Manager

Bengaluru

10 - 15 yrs

INR 20 - 25 Lacs

Staff Digital Design Engineer

Bengaluru

Experience: Not specified

INR 16 - 18 Lacs

Mock Interview

Practice Video Interview with JobPe AI

Start Python Interview

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.