Full chip RTL Design Architect

You are a highly skilled and experienced Full Chip RTL Design Architect sought by the company to join their dynamic team. Your role involves a deep understanding of RTL (Register-Transfer Level) design, SoC (System-on-Chip) architecture, and a passion for innovation in semiconductor design. You will be pivotal in defining and implementing full chip-level RTL designs to ensure successful execution. - Define and develop full chip architecture and RTL designs for complex SoCs. - Drive top-level integration of IPs and subsystems into full chip designs, ensuring design quality and efficiency. - Collaborate on micro-architectural specifications and ensure seamless implementation. - Develop and optimize RTL design methodologies to enhance quality, performance, and power efficiency. - Lead RTL design reviews and offer technical guidance to design teams. - Ensure compliance with coding standards, quality metrics, and verification requirements. - Work closely with system architects, verification engineers, physical design teams, and software developers to align design specifications and deliverables. - Provide feedback and solutions to cross-functional teams to resolve design challenges at all levels of the chip hierarchy. - Mentor and guide junior RTL engineers and team members, fostering a culture of technical excellence. - Stay updated with advancements in RTL design tools, methodologies, and technologies to enhance design practices. - Support pre-silicon verification efforts and collaborate with verification engineers to develop comprehensive test plans. - Analyze simulation results, debug issues, and ensure that the design meets all functional, timing, and power requirements. - Identify and resolve bottlenecks in design performance, power, and area (PPA). - Perform trade-off analysis and optimize designs for efficiency at the system level. - Education: Bachelor's or Masters degree in Electrical Engineering, Computer Engineering, or a related field. - 15+ years of experience in RTL design, SoC architecture, and integration. - In-depth knowledge of RTL design languages such as Verilog and SystemVerilog. - Experience with low-power design techniques and power optimization. - Expertise in debugging tools, synthesis, timing analysis, and simulation. - Familiarity with design-for-test (DFT), design-for-debug (DFD), and physical design constraints. - Strong analytical and debugging skills, with the ability to resolve complex technical issues. - Excellent verbal and written communication skills, with the ability to collaborate effectively across teams.,