Formal Verification Engineer

 
Project Role :Formal Verification Engineer
Project Role Description :Ensure design correctness using mathematical methods like model checking and equivalence checking, without relying on simulation. Detect corner-case bugs early in the design cycle to improve quality and reduce verification time.
Must have skills :SoC Verification
Good to have skills :NA
Minimum 12 year(s) of experience is requiredEducational Qualification:15 years full time education
SummaryAs a Formal Verification Engineer, you will ensure design correctness using mathematical methods such as model checking and equivalence checking. Your role involves analyzing design specifications, developing formal models, and applying verification techniques to detect corner-case bugs early in the design cycle—ultimately improving quality and reducing verification time.Roles & ResponsibilitiesExecute full chip verification cycle:test planning, writing verification code, running tests, RTL debug, and achieving verification closure.Create and utilize verification components and environments based on standard verification methodologies.Collaborate with design engineers to debug tests and deliver functionally correct design blocks.Professional & Technical SkillsExperienced Chip Verification Engineer with 7–10+ years of expertise.Strong understanding of formal verification techniques and methodologies.Additional InformationProficiency in SystemVerilog/UVM or Specman/E.Preferred:Hands-on experience in full-chip verification of large SoC designs. Qualification 15 years full time education