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TekWissen
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DV Engineer Very good in Ethernet, SV & UVM

DV Engineer Very good in Ethernet, SV & UVM

TekWissen

6 - 10 years

0 Lacs

Bengaluru

Posted:2 months ago| Platform:

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Skills Required

debug tools pre-silicon verification Verification Engineer Python/Perl/TCL. ASIC/IP/SoC verification

Work Mode

Work from Office

Job Type

Full Time

Job Description

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Engineer Very good in Ethernet, SV & UVM Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Experienced Design Verification Engineer with a minimum of 6 years in pre-silicon verification. The ideal candidate will have strong hands-on experience with SystemVerilog, UVM methodology, and a solid understanding of SoC/IP-level verification flows. This role involves working closely with design, architecture, and post-silicon teams to ensure high-quality and robust product delivery. Key Responsibilities: Develop testbenches, testcases, and verification components using SystemVerilog and UVM. Create and execute detailed verification plans based on design and architecture specifications. Drive constrained-random verification, coverage closure, and debug failures. Collaborate with RTL, DFT, and Firmware teams to debug issues and ensure seamless integration. Build reusable, scalable, and modular verification environments. Analyze code coverage, functional coverage, and provide meaningful feedback for design improvements. Perform assertion-based verification and support formal verification where required. Participate in code reviews, test plan reviews, and contribute to process improvements. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electronics. 6+ years of experience in ASIC/IP/SoC verification. Must have good knowledge on the verification flows Experience developing testbenches for block level or IP level or SOC Level verification. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Developing and maintaining block level test benches Proficient in SystemVerilog, UVM, and testbench architecture. Strong knowledge of AMBA protocols (AXI, AHB, APB). Hands-on experience with simulation tools (VCS, Questa, XSIM, etc.). Familiarity with debug tools (Verdi, DVE) and waveform analysis. Solid understanding of functional coverage, assertions, and scoreboarding. Experience in writing automation scripts using Python/Perl/TCL. TekWissen Group is an equal opportunity employer supporting workforce diversity.

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DV Engineer Very good in Ethernet, SV & UVM