7 Verification Engineer Jobs

As an experienced HDL design/verification engineer at Lattice Semiconductors, you will play a pivotal role in designing, developing, and enhancing simulation capabilities within Lattice Radiant, the official FPGA design tool. Working closely with hardware developers and QA teams, you will be responsible for enabling and supporting simulation workflows for Verilog, VHDL, and SystemVerilog across various Lattice FPGA families. Your key responsibilities will include diagnosing and resolving simulation issues, validating and testing simulation features, contributing to automation scripts and testbench generation tools, as well as maintaining simulation documentation, troubleshooting guides, and user tutorials. You will have the opportunity to work on cutting-edge technologies and have a direct impact on the evolution of FPGA development tools and methodology. To excel in this role, you must possess a Bachelor's or Master's degree in Electronics Engineering or a related field, along with solid experience in hardware description languages (HDLs) and simulation tools such as Modelsim and Synopsis VCS. A strong understanding of HDL simulation concepts, EDA tool development, FPGA architectures, and configuration flows is essential. Industrial experience in a similar field for more than 5 years is a requirement. Preferred skills for this role include strong analysis and debugging capabilities, as well as excellent communication and cross-disciplinary collaboration skills. In return, Lattice Semiconductors offers competitive compensation, comprehensive benefits, a highly collaborative and intellectually driven team environment, and supportive cross-geo team environment with technical mentorship. If you thrive in a fast-paced, results-oriented environment and are looking to contribute to a dynamic team, Lattice Semiconductors may be the perfect fit for you.,

We are hiring on below Design Verification Engineer/ RTL Design Engineer - Engineer/Lead/Senior Lead . Please find the JD Details below - Please share us your details below in Table with your update resume. Job Descriptions : Please specify for which role your application is for - DV/RTL JD - Design Verification Engineer - Engineer/Lead/Senior Lead JD - RTL Design Engineer- Engineer/Lead/Senior Lead Qualifications: Bachelors degree in electrical engineering, Computer Engineering, or a related field (masters degree a plus) Experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Qualifications: Bachelor’s degree in electrical engineering, Computer Engineering, or a related field (Master's degree a plus) Experience in RTL design for ASICs/SoCs Proven experience in designing and verifying complex digital circuits Proficiency in Verilog or VHDL Experience with verification methodologies (e.g., UVM) Strong understanding of digital design concepts (combinational logic, sequential logic, state machines) Experience with SDC (Standard Delay Constraint) format for timing closure Experience with scripting languages (e.g., Python, Perl) is a plus Excellent communication, teamwork, and problem-solving skills Benefits: Competitive salary and benefits package Opportunity to work on cutting-edge technologies Collaborative and fast-paced work environment Potential for professional growth and development

As a highly experienced Verification Engineer at our dynamic team, you will drive innovation in advanced verification methodologies for complex semiconductor designs. Your key responsibilities will include leading the deployment of verification tools, platforms, and strategies for complex IPs, driving simulation-based and hardware-assisted verification efforts, applying expertise in various verification technologies, developing and enhancing verification methodologies, collaborating cross-functionally with IP design and DV teams, and mentoring junior engineers to foster a culture of technical excellence. You should have 10+ years of experience in verification engineering for complex hardware systems, deep expertise in simulation and debug, hands-on experience with Static/Formal verification tools and methodologies, exposure to hardware-assisted verification environments, strong analytical and problem-solving skills, a degree in Electrical Engineering, Computer Engineering, or related field, familiarity with industry-standard verification languages, experience with scripting and automation, and a track record of technical leadership and cross-functional collaboration. Join our team at Synopsys and be part of an environment that values agility, courage, excellence, and trust. You will have the opportunity to work on cutting-edge technology and make a real impact.,

Job Description : We are looking for experienced DV Engineers with a strong background in ARM-based SoC and Subsystem Verification to join our team for exciting semiconductor projects. Key Responsibilities : Perform Design Verification of ARM-based SoC / SS level components Work on Cortex-A / Cortex-M series SoC Debug using CoreSight infrastructure (implementation or validation) Handle RTL / GLS regressions and perform deep simulation-level debugging Develop or maintain testbenches, checkers, and scoreboards in SystemVerilog/UVM Implement C/C++ modeling as needed for verification environments Technical Skills Required : Strong hands-on in SystemVerilog, UVM Experience with ARM protocols : AXI, AHB, APB, CHI, ACE Solid debugging in NoC, memory subsystems Proficiency in C/C++ Exposure to GLS (Zero delay, SDF, PA GLS) simulations is a plus Knowledge of memory protocols: LPDDR4, LPDDR5, DDR, HBM preferred Experience in PCIe, CXL, Ethernet protocols is a plus Scripting (Python, Perl) – good to have for automation and flow enhancements Desired Candidate Profile : 5+ years of experience in DV Must be proactive , with strong debugging & simulation skills Capable of working independently or as part of a dynamic team How to Apply : Email your CV to: Richa.smriti@orcapod.work , contact: +91 92349 19275

5+ exp in verification at IP/sub-system level. Well versed in (Digital design, SV, UVM). Experience in DDR, PHY protocols. Responsibilities: Develop and execute comprehensive verification plans and testbenches. Write high-quality, efficient, and reusable verification components. Create and maintain detailed verification documentation. Debug complex verification issues and propose solutions. Collaborate with design engineers to ensure design quality and performance. Stay up-to-date with the latest verification methodologies and tools.

Well versed in (Digital design, SV, UVM). Experience in DDR, PHY protocols. Responsibilities: Develop and execute comprehensive verification plans and testbenches using UVM methodologies. Write and debug complex SystemVerilog test code for functional, performance, and regression testing. Collaborate with design engineers to understand and analyze design specifications. Identify, debug, and isolate design issues. Participate in design reviews and contribute to design improvements. Maintain and enhance existing verification environments. Stay abreast of the latest verification methodologies and tools.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Engineer Very good in Ethernet, SV & UVM Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Experienced Design Verification Engineer with a minimum of 6 years in pre-silicon verification. The ideal candidate will have strong hands-on experience with SystemVerilog, UVM methodology, and a solid understanding of SoC/IP-level verification flows. This role involves working closely with design, architecture, and post-silicon teams to ensure high-quality and robust product delivery. Key Responsibilities: Develop testbenches, testcases, and verification components using SystemVerilog and UVM. Create and execute detailed verification plans based on design and architecture specifications. Drive constrained-random verification, coverage closure, and debug failures. Collaborate with RTL, DFT, and Firmware teams to debug issues and ensure seamless integration. Build reusable, scalable, and modular verification environments. Analyze code coverage, functional coverage, and provide meaningful feedback for design improvements. Perform assertion-based verification and support formal verification where required. Participate in code reviews, test plan reviews, and contribute to process improvements. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electronics. 6+ years of experience in ASIC/IP/SoC verification. Must have good knowledge on the verification flows Experience developing testbenches for block level or IP level or SOC Level verification. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Developing and maintaining block level test benches Proficient in SystemVerilog, UVM, and testbench architecture. Strong knowledge of AMBA protocols (AXI, AHB, APB). Hands-on experience with simulation tools (VCS, Questa, XSIM, etc.). Familiarity with debug tools (Verdi, DVE) and waveform analysis. Solid understanding of functional coverage, assertions, and scoreboarding. Experience in writing automation scripts using Python/Perl/TCL. TekWissen Group is an equal opportunity employer supporting workforce diversity.