Design Engineer II

As an Electrical Validation Engineer at Cadence, you will be responsible for post-silicon physical layer validation on high-speed SERDES protocols such as PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO, etc. Your role will involve utilizing lab equipment like Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT), and more to conduct deep validation testing. Key Responsibilities: - Perform physical layer electrical validation on high-speed SERDES protocols - Utilize lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) - Manage small teams and lead post-silicon validation efforts for projects - Design FPGA, PCB schematic and layout, and prototype development - Conduct pre-silicon IP/SoC physical layer electrical validation for board bring-up and debug - Utilize Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL - Conduct hiring interviews and mentor new hires Qualifications Required: - 2-4 years of experience with Btech or 1-2 years with Mtech in Post-Silicon Physical Layer Electrical Validation - Experience in managing small teams and leading validation efforts - Knowledge of FPGA Design, PCB schematic and layout design, and Prototyping - Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL - BE/BTech/ME/MTech or equivalent qualification At Cadence, you will be part of a team that is dedicated to solving challenges that others cannot. Join us in making a meaningful impact in the world of technology.,