ASIC RTL Integration Manager, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
• 15 years of experience in ASIC RTL design integration.
• Experience in Verilog or Systemverilog coding.
• Experience in High performance design, Multi power domains with clocking of multiple SoCs with silicon.
  

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
• Experience with Application-Specific Integrated Circuit (ASIC) design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, Design for testing (DFT) ATPG/Memory BIST, Unified Power Format (UPF) and Low Power Optimization/Estimation.
• Experience with chip design flow and understanding of cross domain involving DV DFT/Physical Design/software.
• Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.
  

About the job

Responsibilities

• Lead a team of ASIC Register-Transfer Level (RTL) engineers on Sub-system and chip-level Integration activities including planning tasks, hold code and design reviews, code development of features.
• Interact closely with the architecture team and develop implementation (e.g., microarchitecture and coding) strategies to meet quality, schedule and Power Performance Area (PPA) for Sub-system/chip-level integration.
• Work with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.