Analog Design, Sr Supervisor

The role at Synopsys revolves around being at the forefront of cutting-edge innovations that are reshaping the way businesses operate and individuals engage in leisure activities. Whether it's self-driving vehicles, Artificial Intelligence, the cloud, 5G, or the Internet of Things, these advancements are heralding the Era of Smart Everything. Synopsys is driving this transformation with the most sophisticated technologies for chip design and software security. If you are driven by the same enthusiasm for pioneering solutions, we are eager to connect with you. Within our Silicon IP division, our focus lies in enhancing System on Chip (SoC) integration at a rapid pace. We possess the largest array of silicon IP globally, comprising pre-designed logic blocks, memory components, interfaces, analog features, security modules, and embedded processors. Our goal is to assist clients in incorporating more functionalities into their products, meeting specific performance, power, and size criteria for their intended applications, and expediting the launch of distinctive products to market with minimized risks. We are currently seeking forward-thinking professionals to lead the development of our upcoming generation of DDR/HBM/UCIe PHY IPs. Responsibilities: - Serve as a Senior Supervisor to spearhead the progress of the next generation of DDR/HBM/UCIe IP - Exhibit leadership attributes by driving the development of new technologies, showcasing adept analytical and problem-solving skills - Offer guidance to team members to adhere to schedules and address challenges effectively - Play a pivotal role in project management and contribute to the intricate facets of a project - Create and uphold schedules, collaborate across diverse teams, and exhibit proficiency in design and verification processes Requirements: - Qualification: BTech/MTech - Skills/Experience: 8+ years - Proficiency in CMOS processes and challenges in deep submicron process technologies - Sound understanding of CMOS circuit design and layout methodology, comprehensive knowledge of analog/mixed-signal circuitry, and familiarity with basic ESD principles is advantageous - Well-versed in analog mixed-signal simulation strategies, with a solid grasp of Signal Integrity and/or Power Integrity being beneficial - Acquainted with ASIC design flow - Familiarity with JEDEC requirements for DDR interfaces and standards, DDR Timing, ODT, and SDRAM functionality would be advantageous - Capable of leading projects to deliver top-notch product quality and operational efficiency - Excellent written and verbal communication skills to effectively engage with development teams,