AMS Verification Engineer - System Verilog

As an AMS Verification Engineer, you will play a crucial role in ensuring the functionality and quality of Analog Mixed Signal (AMS) designs. Your role will involve the following responsibilities: - Developing and executing verification plans for AMS designs to validate their functionality. - Creating and automating testbenches for AMS verification to enhance the efficiency of the verification process. - Building and maintaining SystemVerilog real number models to accurately represent the AMS designs. - Collaborating with analog and digital design teams to ensure that the designs meet the required specifications. - Verifying the functionality of AMS/DMS IP/chip to guarantee its performance. To excel in this role, you should possess the following skills: - Strong RNM modeling skills to effectively model the behavior of analog and mixed-signal components. - Proficiency with Cadence AMS/DMS flow to work seamlessly within the design environment. - Experience with SystemVerilog and Verilog-AMS to develop verification environments. - Knowledge of analog and mixed-signal design principles to understand the intricacies of AMS designs. - Familiarity with UVM (Universal Verification Methodology) to implement robust verification methodologies. - Ability to debug AMS modeling issues to identify and resolve verification challenges. - Experience with basic scripting/automation to streamline verification tasks. - Good communication and documentation skills to effectively communicate with team members and document verification processes. If you have more than 5 years of experience in AMS verification, hands-on RNM modeling exposure, and the required skills mentioned above, and are enthusiastic about contributing to a dynamic team, we would like to hear from you.,