2891 Verilog Jobs - Page 40

As a member of the Cadence team, you will have the opportunity to contribute to the world of technology by designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your responsibilities will include designing and implementing RTL for DFT IP, including POST and IST. You will play a key role in developing synthesis automation for DFT IP, which involves synthesis and timing constraints, RTL insertion, and verification. Additionally, you will be responsible for owning, maintaining, extending, and enhancing existing DFT IP such as LBIST. Join us in our mission to make a difference in the technology industry. Be a part of our team and help us tackle challenges that others cannot.,

Qualcomm India Private Limited is a company of inventors at the forefront of 5G technology, unlocking new possibilities that will revolutionize industries, create job opportunities, and enhance lives. As part of the Engineering Group in the Hardware Engineering division, you will be joining a dynamic team responsible for designing Low Power controller IP cores and subsystem digital design for cutting-edge Snapdragon SoCs used in mobile, compute, IoT, and Automotive markets globally. In this role based at Qualcomm's Bangalore office, your key responsibilities will include micro-architecture and RTL design for Cores/subsystems, collaborating closely with Systems, Verification, SoC, SW, PD & DFT teams, enabling software teams to utilize hardware blocks, qualifying designs through static tool checks, and reporting progress status against expectations. Preferred qualifications for this position include 5 to 10 years of experience in digital front-end design (RTL design) for ASICs, expertise in RTL coding in Verilog/SV/VHDL, familiarity with UPF and power domain crossing, experience in synthesis, logical equivalence checks, RTL and netlist CLP, proficiency in various bus protocols, low power design methodology, clock domain crossing designs, formal verification, and database management flows. Additionally, expertise in Perl/TCL/Python language, post-Si debug, and strong communication skills are valued qualities for this role. To be considered for this opportunity, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 4+ years of Hardware Engineering experience, or a Master's degree with 3+ years of relevant work experience, or a PhD with 2+ years of related work experience. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities during the application/hiring process. Please reach out to disability-accommodations@qualcomm.com for support. The company expects its employees to comply with all applicable policies and procedures, including confidentiality requirements. If you are a staffing or recruiting agency, please note that Qualcomm's Careers Site is exclusively for individual job seekers, and submissions from agencies will be considered unsolicited. For more information about this role, please contact Qualcomm Careers directly.,

NVIDIA is a company that has continually reinvented itself, with a rich history that includes inventing the GPU, which transformed the PC gaming market and modern computer graphics. The company has also played a pivotal role in revolutionizing parallel computing. Today, the field of artificial intelligence is experiencing rapid growth globally, necessitating highly scalable and massively parallel computation power, an area in which NVIDIA GPUs excel. NVIDIA is committed to evolving and adapting to new challenges that are unique, complex, and impactful on a global scale. The company's mission is to enhance human creativity and intelligence, making a lasting impact on the world. Joining NVIDIA means becoming part of a diverse and supportive environment where individuals are encouraged to strive for excellence in their work. As an NVIDIAN, you will have the opportunity to work with a team that is dedicated to designing, implementing, and debugging the next generation of GPUs, SOCs, and system simulation environments. Your role will involve developing the core verification infrastructure for a full-system platform used in the development of discrete graphics and computing chips. This will entail utilizing object-oriented C++ and System-C simulation infrastructure to model and verify some of the world's largest chips through a distributed-computing-based execution and triage environment. As a member of our team, you will be responsible for creating environments to model and simulate future GPU and SoC systems, integrating features well before they are physically built or implemented in driver software. You will collaborate with architecture and engineering teams to optimize the functionality and performance of upcoming NVIDIA chips. Our team is involved in every stage of chip development, from architectural specification to verification and production. To be successful in this role, you should hold a Bachelor's or Master's degree in computer science/computer engineering or possess equivalent experience. Additionally, you should have at least 4 years of experience in professional object-oriented C++ programming and System-C simulation/modeling. Familiarity with Transaction Level Modeling and Verilog/System Verilog is advantageous, as is experience in RTL simulation. Knowledge of software development lifecycle on Linux-based platforms and an understanding of computer and memory system architecture are preferred. Strong communication skills are essential, as you will collaborate with colleagues from diverse backgrounds on a regular basis. NVIDIA offers competitive salaries and a comprehensive benefits package. The company is home to some of the most talented and hard-working individuals globally, and due to rapid growth, our engineering teams are expanding. If you are a creative, autonomous engineer with a genuine passion for technology, we invite you to join our diverse, international, and fast-paced team at NVIDIA and contribute to the development of next-generation products adhering to the highest production-quality standards.,

Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is seeking highly motivated and talented professionals for its R&D center in Bengaluru to be a part of the world-class team. Eridu AI is a Silicon Valley hardware startup with a primary focus on accelerating training and inference performance for large AI models. The company introduces innovative solutions across semiconductors, software, and systems to enhance AI data center performance by increasing GPU utilization while reducing capex and power consumption. Eridu AI's value proposition has been widely recognized by several hyperscalers. The leadership team of Eridu AI comprises Silicon Valley executives and engineers with extensive experience in semiconductors, optics, software, and systems. The company is led by Drew Perkins, a serial entrepreneur with a successful track record in various tech ventures. As a RTL Data Path Engineer at Eridu AI, you will play a crucial role in defining and implementing the Networking IC. This is a unique opportunity for self-starters who are passionate about solving real-world problems and shaping the future of AI Networking. You will be responsible for designing, specifying, architecting, executing, and productizing cutting-edge Networking devices. Key Responsibilities: - Data Path Design: Design and architect solutions for high-speed networking devices with a focus on latency optimization, memory management, and QoS support. - Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Conduct thorough testing and validation. - Performance Optimization: Analyze and optimize memory/buffering for improved performance metrics. - Protocol Support: Provide support for various networking protocols and standards related to input and output queues, including Ethernet. - Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, collaborating with cross-functional teams. Qualifications: - BE/ME with 8-15 years of experience. - Proficiency in system Verilog and Verilog is mandatory. Previous experience with memory subsystem ownership. - Expertise in designing and optimizing memory algorithms and QoS mechanisms for high-speed networking devices. - Solid understanding of ASIC design methodologies and verification tools. - Experience with Ethernet/PCIe networking protocols. - Strong analytical and problem-solving skills with attention to detail. - Excellent communication skills and ability to work effectively in a team environment. Join Eridu AI to be part of a team that is shaping the future of AI infrastructure with groundbreaking technology. Your work will directly impact the evolution of AI networking solutions and data center capabilities. The starting base salary will be determined based on relevant factors.,

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary We know our employees’ ideas change the world. For more than three decades, we’ve been a global leader in mobile technology, continually pushing the boundaries of what’s possible. Working with customers across industries — from automotive to health care, from smart cities to robotics— we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. Qualcomm is looking for an energetic, creative and self-driven engineer to work in Modem , Multimedia , Connectivity , Computer Vision and Image Processing , software implementation and hardware acceleration. The work will directly influence the various subsystems within the SoC. The ideal candidate would have very strong problem solving and analytical skills combined with creativity and a passion for innovation. They would be able to carry forward that new idea, concept, and/or application that will propel systems to new levels of effectiveness and efficiency. At Qualcomm you will perform detailed technical analysis, translate ideas into models, SW and/or HW and work closely with other teams to help deliver real products. At Qualcomm, the sky's the limit. College Graduates play important roles everywhere in the company. Many of our 27,000+ employees join us right out of school because we're working on the cutting edge in wireless. Complex wireless devices are only as powerful as the software that runs them. As a software engineer, you will develop, implement and maintain multimedia, gaming and application software for the world's leading-edge mobile devices. We know our employees’ ideas change the world. For more than three decades, we’ve been a global leader in mobile technology, continually pushing the boundaries of what’s possible. Working with customers across industries — from automotive to health care, from smart cities to robotics— we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design\ Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Educational Background Masters, Bachelors: Electrical Engineering , VLSI , Embedded and VLSI , ECE Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3078320

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : PySpark Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Developer, you will design, build, and configure applications to meet business process and application requirements. A typical day involves collaborating with team members to understand project needs, developing application features, and ensuring that the solutions align with business objectives. You will also engage in problem-solving discussions and contribute to the overall success of the projects by leveraging your expertise in application development. Roles & Responsibilities:- Expected to be an SME.- Collaborate and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Facilitate knowledge sharing sessions to enhance team capabilities.- Monitor project progress and ensure timely delivery of application features. Professional & Technical Skills: - Experience should be 6+ years in Pyspark.- Candidate must be a strong Hands-on senior Developer- As a lead, should be able to support team on technical issues and status tracking- Candidate must possess good technical / non-technical communication skills to highlight areas of concern/risks- Should have good troubleshooting skills to do RCA of prod support related issues- Prior experience working with senior client stakeholders is preferable. Additional Information:- The candidate should have minimum 5 years of experience in PySpark.- This position is based at our Bengaluru office.- A 15 years full time education is required.- Candidate must be willing to work in Shift B i.e. from 11 AM IST to 9PM IST. Also, do the weekend support as per a pre-agreed rota. Compensation holiday may be provided for the weekend shift. Qualification 15 years full time education

Role Overview As a Lead Design Verification Engineer , you will own verification strategy and execution for high-complexity IP and SoC designs. You will be responsible for planning, leading teams, defining testbench architecture, and ensuring coverage-driven closure. Key Responsibilities Define and drive the verification plan based on design specifications and functional requirements. Architect and develop reusable UVM/SystemVerilog-based testbenches. Own IP/SoC-level functional verification from test planning to coverage closure. Work closely with RTL, DFT, and firmware teams for seamless integration and debug. Guide and mentor junior engineers; conduct reviews and knowledge sessions. Contribute to verification methodology improvements and best practices. Perform regression setup, coverage analysis, and issue tracking. Deliver high-quality, first-time-right silicon. Required Skills Strong experience in IP/SoC verification using SystemVerilog/UVM . Solid understanding of verification methodologies and simulation flows. Hands-on with tools like VCS, Questa, Verdi, SimVision, etc. Experience with standard bus protocols like AXI, AHB, PCIe, USB, etc. Good debugging skills using waveform viewers and log analysis. Experience in writing assertions and functional coverage models. Knowledge of scripting (Python, Perl, TCL) is a plus. Strong communication and leadership abilities. Preferred Qualifications Experience with formal verification, assertion-based verification (SVA). Exposure to low-power verification and UPF flows. Familiarity with safety/security standards (e.g., ISO 26262, DO-254). Experience working with emulation platforms and FPGA prototyping. Location: Bangalore / Hyderabad / Pune Experience: 815 Years Notice Period: Immediate to 30 Days Company: ADV Logics – Empowering Next-Gen VLSI Innovation

CPU Performance Validation Engineer THE ROLE: The person will be part of AMDs CPU Performance Validation team. This team is part of AMDs global CPU Performance teams and plays a critical role in next generation AMD CPU design. Involves having deep understanding of existing AMD X86 CPU architecture and microarchitecture ranging from CPU pipeline stages to various complex features and structures, debugging performance issues of RTL, giving feedback to design team for latest gen CPU in pre-silicon and emulation environment. We highly encourage people with a creative bent of mind and with a natural ability to dive into the details. This team is a perfect place for people who can understand the present and envision the future. If you find yourself to be a person who wants to go that extra mile to refine an existing process and also understands the opportunities to make it better, if you are the one who has innovative ideas in your brain waiting to find a proper stage to come out, we can offer you the perfect ground for that. THE PERSON: Should have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment. Continuous learning has always been the moto in this ever changing industry. An ideal person for this role should be a self-learner and always ready to upgrade his/her skills to stay abreast with the technology. The team looks for superstars but also believes in nurturing you into one. Collaboration is the key to success. Ideal candidate should learn at a great pace, deliver what is expected and also share your learning in the team to help the overall growth. It s always We before Me in the team KEY RESPONSIBILITIES: Responsible for building infrastructure for performance verification and verify performance of X86 processor. Writing specific targeted tests to measure the performance of the processor Involves having a deep understanding of processor micro-architecture and triaging performance issues in RTL and simulator Skillset Debug triage of failures from simulation and emulation environment for CORE or sub level regressions. Writing automatized triages in Perl/Ruby and creating tools using perl/ruby or AMD verification methodology (primarily in C++) to enhance the functional debug and triage process. On a need basis, work on Post-Si bug recreation PREFERRED EXPERIENCE: Experience: 2-5 years experience in processor/ASIC performance correlation. Experience in micro-architecture testing for modern high-performance processors. Experience in writing tests and building infrastructure that tests performance of modern processors. Experience in application performance analysis Programming/Scripting Skills C, C++, Perl, Python. Solid background and understanding of Digital Design, RTL design , improving model performance and Processor Architecture Strong troubleshooting, analytical and debug skills. Prior experience in performance correlation of Processor subsystems is a plus. Excellent knowledge of computer architecture with relevant research and project work or industry experience Strong programming skills (C/C++ and assembly) Basic knowledge of Verilog ACADEMIC CREDENTIALS: Bachelors/Masters in Computer Science/Electrical/Electronics Engineering with relevant course and research work LOCATION: Bangalore #LI-RR1 #LI-Hybrid AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

Job title: FPGA Design Engineer (Telecom/Aerospace) Organization Name: NEC Corporation of India Ltd. Reporting Relationship: Reporting to Project Manager Location: Chennai/Hybrid Experience 1 -2 years Job Summary: We looking for an experienced and highly talented FPGA design engineer with strong telecom and Aerospace expertise at NEC Mobile Network Excellence Center (NMEC), Chennai Scope of work Implementing FPGA code on the target hardware & testing with other system components and software RTL Design, Implementation, Testing, Integration and delivery of FPGA based hardware systems for Telecom and Aerospace Applications Involve in R&D activities demonstrating Proof of Concept in various technologies for aerospace related design techniques. Qualifications BE/B.Tech/M.E/M.Tech or its Equivalent Experience 1 -2 years Domain Expertise Proficient in FPGA design flows using Xilinx tools, including compilation, simulation, synthesis, debugging, performance optimization, and implementation of advanced features. Strong knowledge of hardware description languages such as Verilog, VHDL, and System Verilog. Skilled in developing verification environments using self-checking testbenches, Bus Functional Models (BFMs), checkers/monitors, and scoreboards in VHDL/Verilog. Familiarity with designing common control interfaces such as AMBA AXI, UART, SPI, I C, DDR, Ethernet, and USB. Hands-on experience with hardware measurement and debugging tools including oscilloscopes, signal analyzers, and JTAG emulators. Good to Have Experience integrating Soft IP or Hard IP like GTX/GTH transceivers, MAC, DMA controller, PCIe Gen3, CPRI, JESD, or FFT IP cores Proficiency in scripting languages for automation, including Perl, TCL, or Python. Exposure to standard FPGA hardware bring-up procedures and testing methodologies. Experience in linting, static timing analysis, equivalence checking, and clock domain crossing (CDC) verification.

Roles and Responsibility Experience: 6 - 15 years Responsibilities: Verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx/AI accelarator integration verification in SoC RTL. Your key responsibilities will include writing test plans, defining test methodologies, developing C based software tests, SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience : Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies - UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures, SoC Boot flow, Cache coherency Porting peripheral driver software for SoC tests Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.)

Design Verification Engineer (5 + years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-+ years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement e & responsibilities

Hiring now Criteria - B.Tech below 2022 and M.Tech below 2024 Location - Bangalore Preferred Engineers who have completed their Training in #VLSI domains for below requirements #PD #AL #RTL #DFT Share profiles to kartikchandu@juntrantech.com Health insurance Provident fund

Apply now » Senior Technical Lead Company: NEC Corporation India Private Limited Employment Type Office Location: Kandanchavadi, Perungudi, TN, IN, 600096 Work Location: Hybrid Req ID: 4517 Description Reporting Relationship: Reporting to Project Manager Job Summary NEC Corporation India Pvt. Ltd is looking for an experienced and highly talented FPGA Lead with strong telecom and Aerospace expertise at NEC Mobile Network Excellence Center (NMEC), Chennai Scope of work Implementing FPGA code on the target hardware & testing with other system components and software RTL Design, Implementation, Testing, Integration and delivery of FPGA based hardware systems for Telecom and Aerospace Applications Interaction with various vendors/ OEMs to identify the right solution Co-work with internal/external engineering team on Hardware, RF, Mechanical and Software team etc. Involve in R&D activities demonstrating Proof of Concept in various technologies for aerospace/ defence related design techniques. Qualifications BE/B.Tech/M.E/M.Tech Or Its Equivalent Experience 8+ years Domain Skills Expert in FPGA flows with Xilinx, including compilation, synthesis, debug, performance and implementation of advanced features Good Hands on Linting, Static Timing Analysis, Equivalence Checking & Clock Domain Crossing. Experience in developing verification environment to verify developed items using self-checking test benches, BFMs, checkers/Monitors & Score boards using VHDL/verilog. Prior experience in integrating Nios, MPIS, MicroBlaze, ARM Cortex, etc. GTX / GTH transceivers & 10GE MAC / DMA controller / PCIe Gen3 / CPRI / JESD / FFT IP core Common control interfaces design, like AMBA AXI, UART, SPI, I2C, DDR, Ethernet, USB, etc.. Knowledge on programming languages such as Verilog, VHDL and system Verilog Experience with any scripting language for automation (Perl/TCL/Python). Familiar with standard FPGA HW bring-up activities and testing Experience with HW measuring tools like oscilloscopes, Signal analysers, JTAG Emulators Specialization Description Responsible for improving or developing new products, components, equipment, systems, technologies, or processes including: Ensuring that research and design methodologies meet established scientific and engineering standards Assisting with formulating business plans and budgets for product development Analyzing quality/safety test results to ensure compliance with internal and external standards Keeping abreast of new developments in the industry and translating those developments into new and viable options for the organization and customers Organizing technical presentations to customers and/or industry groups Monitoring product development outcomes to ensure technical, functional, cost, and timing targets are met In some organizations, may be responsible for managing product regulatory approval process Level Description Experienced level professional that applies practical knowledge of job area typically obtained through advanced education and work experience. Works independently with general supervision. Works to achieve operational targets within the job area with a direct impact on function / sub-function results. Problems faced are difficult but typically not complex. May influence others within the job area through explanation of facts, policies and practices. Headquartered in Japan, NEC is a leader in the integration of IT and network technologies. With over 123 years of expertise in providing solutions for empowering people, businesses, and society, NEC stands tall as a champion in enabling change and transformation across the globe. Present in India since 1950, NEC has been instrumental in burgeoning India’s digitization journey continually for the past 70 years. NEC India has proved its commitment to orchestrating a bright future through its diverse businesses from Telecommunications to Public Safety, Logistics, Transportation, Retail, Finance, Unified Communication and IT platforms , serving across the public and private sectors. NEC India, through the deployment of cutting-edge technology, has been powering India in seminal ways, making lives easier, safer, and more productive for all. With its Centre of Excellence for verticals like Analytics platform solutions, Big Data, Biometrics, Mobile and Retail , NEC India brings to the table, innovative, seamless solutions for India and across the world. NEC India is headquartered in New Delhi and has its offices panned across the country. It has branches in Ahmedabad, Bengaluru, Chennai, Mumbai, Noida and Surat. Specialties IT & Networking Solutions, Unified Communication Solutions, Safety and Security Solutions, Integrated Retail Solutions, Data Centre Solutions, Safe and Smart City Solutions, Transportation Solutions, SDN Solutions, Carrier Telecom Solutions, and Solutions for Society. NEC Career Site - LinkedIn Apply now »

Sr. Silicon Design Engineer Hyderabad, India Engineering 67455 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The FPGA Architecture Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex FPGA architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Looking for experienced candidates who want to make an impact on AMD (Xilinx)’s future FPGA Architectures. An ideal candidate for this position should be good with one or more of the below areas : familiarity with FPGA design flows, qualitative and quantitative comparison of hardware Architectures. This role requires candidates to be able to independently come up with analytical / mathematical or otherwise methods to compare and contrast various aspects (related to power, performance and area) of one generation of FPGA PL architecture to future FPGA architectures. Preferred skills : Verilog, FPGA design flow, HLS, Accelerator, Architecture, Algorithms, C++, Python, Matlab, Linear programming , ML, ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SG AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated ASIC Digital Design Engineer with a relentless passion for innovation and a commitment to excellence. Your deep expertise in digital design and verification is matched by your curiosity and willingness to tackle complex challenges. You have a solid foundation in microprocessor architectures and are adept at developing and maintaining hardware-software co-simulation environments. Your analytical mindset enables you to create comprehensive functional and code coverage models, and you handle regression testing with precision and care. Your technical toolkit is robust: you are fluent in HDL and verification languages such as SystemVerilog and Verilog, and you bring strong programming skills in C, C++, assembly, Python, and Perl. You are comfortable using RTL simulators and verification tools and are always eager to expand your technical horizons by learning new methodologies. Collaboration is second nature to you—you thrive in multi-cultural, multi-time zone teams and foster inclusive teamwork. Your excellent communication skills ensure that your ideas are heard and understood, and you enjoy sharing your knowledge while learning from others. You take pride in delivering high-quality, reliable work, and you are driven by the opportunity to make a meaningful impact on the future of technology. What You’ll Be Doing: Developing and automating advanced testbenches for ARC processor verification processes. Creating and maintaining functional coverage models and analyzing coverage reports for completeness and effectiveness. Performing comprehensive code coverage analysis to ensure thorough verification and identify potential gaps. Integrating both third-party and internal verification IPs into verification environments. Managing regression testing cycles, analyzing results, and ensuring robust test coverage across all features. Collaborating with multi-site and multi-cultural teams to drive next-generation ARC processor verification projects. Contributing to the improvement of verification methodologies and automation flows. The Impact You Will Have: Ensuring the reliability and high performance of next-generation ARC-V processors. Contributing to the delivery of cutting-edge silicon IP solutions that power industry-leading products. Enhancing the efficiency and effectiveness of verification techniques and processes. Reducing time-to-market for high-performance, low-risk products through rigorous verification. Championing collaboration and knowledge sharing across global engineering teams. Helping Synopsys maintain and strengthen its leadership position in the semiconductor industry. What You’ll Need: Bachelor’s degree in engineering or a related technical field (required). 4+ years of experience in digital design and verification, with a proven track record of success. Strong knowledge of digital design principles and methodologies. Proficiency in SystemVerilog, Verilog, C, C++, assembly, Python, and Perl. Hands-on experience with RTL simulators and verification tools. Experience with microprocessor architectures (RISC-V experience is a significant plus). Who You Are: An excellent communicator with strong verbal and written skills. A collaborative team player who thrives in a multi-cultural, multi-time zone environment. Analytically minded with exceptional problem-solving skills and attention to detail. Adaptable and eager to learn new technologies, tools, and methodologies. Self-driven, proactive, and passionate about delivering high-quality, reliable results. The Team You’ll Be A Part Of: You will be a key member of the Synopsys DesignWare ARC Processor hardware team, working alongside talented engineers on next-generation ARC processor verification. The team is dedicated to developing and maintaining advanced verification environments, ensuring the high performance and reliability of our silicon IP solutions. You will collaborate with colleagues across various locations and time zones, contributing to innovative projects that drive the semiconductor industry forward. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: ASIC / IP Verification THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-MK1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: AECG ASIC DFX - SMTS SILICON DESIGN ENGINEER T HE ROLE : AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. As a member of the AECG SSD ASIC Group, you will help bring to life cutting-edge designs. As a member of the DFT design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology. Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS. Writing and maintain DFT documentation and specifications. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. P REFERRED EXPERIENCE : Minimum 12 years of DFT design, integration, verification, ATPG and Silicon Debug experience. Demonstrated technical leadership and works well with cross-functional teams. Excellent communication and interpersonal skills Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues with integration, synthesis and PD teams. Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis. Knowledge of ATE and digital IC manufacturing test is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RP1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job description Company: ARF Design Pvt Ltd Location: Bhubaneswar and Ranchi Employment Type: Full-Time | Permanent Working Days: Monday to Saturday Interview Mode: Face-to-Face Job Description:– Analog Layout Engineer We are actively hiring Analog Layout Engineers with 3+ years of industry experience. Ideal candidates must have solid expertise in lower technology nodes, physical layout techniques, and verification processes. ARF provides an excellent platform to work on advanced nodes with fast-track interview and onboarding processes. Key Responsibilities: ● Design and development of analog layout IP blocks and full-chip integration ● Perform and resolve LVS/DRC violations independently ● Collaborate with circuit design teams to optimize layout quality and performance ● Ensure layouts meet design matching and parasitic constraints ● Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: ● 3+ yrs of relevant Analog Layout experience ● Proficiency in LVS/DRC checks and EDA tools ● Experience with lower technology nodes (3nm,5nm,7nm,10, 16nm / 28nm ETC) ● Good understanding of layout matching, parasitic extraction, and floor planning ● Strong verbal and written communication skills ● Ability to work independently and within cross-functional teams Job Description:– Circuit Design Engineer ARF Design is hiring Analog Mixed Signal Designers to work on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. Key Responsibilities: ● Derive circuit block level specifications from top level specifications ● Perform optimized transistor-level design of analog and custom digital blocks ● Run SPICE simulations to meet detailed specifications ● Guide layout design for best performance, matching, and power delivery ● Characterize design performance across PVT + mismatch corners and reliability checks (aging, EM, IR) ● Generate and deliver behavioral (Verilog), timing (LIB), and physical (LEF) models of circuits ● Conduct design reviews at various phases/maturity of the design Qualifications: ● BE/M-Tech in Electrical & Electronics ● Strong fundamentals in RLC circuits, CMOS devices and digital design concepts (e.g., counters, FSMs) ● Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators ● Collaborative mindset with a positive attitude Exp: 3+ Please share updated resume [Name_Post_Exp] to divyas@arf-desgn.com Job Types: Full-time, Permanent Work Location: In person

Greetings from the Department of Electronics and Communication Engineering, NIT Rourkela. We are pleased to invite applications for the post of Research Fellow (RF) and Project Associates (PA) under a prestigious research project funded by the Department of Telecommunications (DOT), Government of India, titled: 🎯 “Waveform Design, Testing, and Verification for Joint Radar and Communication at Millimeter Wave Frequency Band.” 📌 Key Details: Number of Positions: 03 (RF 1 position, PA 2 position) Duration: Up to December 2027 Monthly Fellowship: ₹45,000/- for RF, ₹22,500/- for PA Mode of Interview: Online Interview Date: August 13, 2025, 10:00 AM Last Date to Apply: August 11, 2025 Department: Electronics and Communication Engineering, NIT Rourkela 🎓 Eligibility Criteria RF: M.Tech/M.E/MS or equivalent in ECE, EE, CSE, RF, Microwave, Telecommunication, Signal processing, AI/ML, VLSI, etc. Or M.Sc./MCA Or B.Tech/B.E with GATE score for RF 🎓 Eligibility Criteria PA: B.Tech/B.E in ECE, EE, CSE, MSc Minimum 60% marks or 6.5/10 CGPA throughout Responsibilities: RF: Conduct research on development of joint radar and communication (JRC) technology. Designing, simulating, and testing of waveform for JRC. Design, validate the concept in SDR/ FPGA module. PA: Develop conceptual hardware to prove JRC concepts. Design and development of millimetre wave hardware for 6G wireless communication as well as radar functionality. Testing and debugging RF and baseband circuits. 🧠 Desired Skills: Strong knowledge at least in two research areas among the following: 1) digital signal processing. 2) Embedded Systems. 3) wireless communication. 4)Antenna Design, 5) RF circuit design, debugging, and testing. Programming proficiency in Python, MATLAB, VHDL/Verilog, etc. Exposure to hardware (SDR, FPGA, RF-Soc) and EDA tools preferred This opportunity also opens avenues for M Tech Research/ Ph.D. admission, subject to eligibility and institute norms. Interested candidates may reach out to the PI: Prof. Subrata Maiti 📧 Email: smaiti@nitrkl.ac.in Advertisement Details can be found in NIT Rourkela website: https://nitrkl.ac.in/SRICCE/Career

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job responsibilities: Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC Create verification environment using UVM methodology Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure. Work with architects, designers, and post-silicon teams Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions including Formal Verification Development of tools for Design and Verification support Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications 3-8 Years of relevant experience - Education: B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering Skills Required/Preferred Software Skills Required: Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable - Functional Verification: Unit/Sub-system/SOC level verification experience Experience in leading verification closure of complex IP/SOC for at least one project Exposure to industry standard verification tools for simulation and debug RTL & Gate Level Simulations Proficiency in Verilog, System Verilog , Assertions and UVM Exposure to Verification Fundamentals Verification Automation using scripts like Python, Perl,shell,tcl/tk Good debugging and problem solving skills. Good communication skills and ability, desire to work as a team player Exposure to Analog verification will additional plus point -Digital design Concepts CMOS VLSI, Digital Circuits Knowledge on Memory (preferred) (SRAM/DRAM/ROM/ Flash ) Circuits/Logic Preferred exposure NCSIM, Xcellium, IMC, IEV, Verdi, Jaspergold, VS Formal Cadence Schematic and layout environment Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job responsibilities: Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC Create verification environment using UVM methodology Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure. Work with architects, designers, and post-silicon teams Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions including Formal Verification Development of tools for Design and Verification support Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications 3-8 Years of relevant experience Education: B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering Skills Required/Preferred (SRAM/DRAM/ROM/ Flash ) Circuits/Logic Software Skills Required: Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable Functional Verification: Unit/Sub-system/SOC level verification experience Experience in leading verification closure of complex IP/SOC for at least one project Exposure to industry standard verification tools for simulation and debug RTL & Gate Level Simulations Proficiency in Verilog, System Verilog , Assertions and UVM Exposure to Verification Fundamentals Verification Automation using scripts like Python, Perl,shell,tcl/tk Good debugging and problem solving skills. Good communication skills and ability, desire to work as a team player Exposure to Analog verification will additional plus point -Digital design Concepts CMOS VLSI, Digital Circuits Knowledge on Memory (preferred) Preferred exposure NCSIM, Xcellium, IMC, IEV, Verdi, Jaspergold, VS Formal Cadence Schematic and layout environment Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job responsibilities: Able to lead IP/Sub-System/Soc Team as Overall Project Functional Lead (PFL) Study industry standard methodologies and quickly implement same in the team Develop test plans, tests and verification infrastructure for complex IP/sub-system/SOC Expertise in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure Create verification environment using UVM methodology Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure. Work with architects, designers, and post-silicon teams Expertise in SVA development like coding, porting and maintaining System Verilog Assertions and Formal Verification Guide junior members , lead projects and manage global stakeholders Define state of the art Logic Verification methodology and participate in innovation and initiatives Development of tools for Design and Verification support. Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications 13+ Years of the relevant work experience Education: B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering Skills Required/Preferred (SRAM/DRAM/ROM/ Flash ) Circuits/Logic Software Skills Required: Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable Functional Verification: Unit/Sub-system/SOC level verification experience Experience in leading verification closure of complex IP/SOC for at least one project Exposure to industry standard verification tools for simulation and debug RTL & Gate Level Simulations, RNM Verification Proficiency in Verilog, System Verilog , Assertions and UVM Exposure to Verification Fundamentals Verification Automation using scripts like Python, Perl,shell,tcl/tk Good debugging and problem solving skills. Good communication skills and ability, desire to work as a team player Exposure to Analog verification will additional plus point -Digital design Concepts CMOS VLSI, Digital Circuits Knowledge on Memory (preferred) Preferred exposure NCSIM, Xcellium, IMC, IEV, Verdi, Jasper, VS Formal, vManager Cadence Schematic and layout environment Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Lead the verification planning and execution for complex SoC designs. Define and implement testbenches using SystemVerilog/UVM methodologies. Work closely with architecture, design, and firmware teams to understand the design and develop test strategies. Drive block-level and full-chip verification , including IP integration . Perform coverage analysis , debug , and triage failures . Develop and maintain automation scripts to improve verification workflows. Mentor and guide junior verification engineers and drive best practices across the team. Ensure delivery on schedule with high quality and coverage metrics.

Design Verification Engineer (5+ years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5+ years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement

Embedded Domain RTL/FPGA Design Engineer(Fresher) Min 0 - 3 Years of Experience BE/B.Tech in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or closely related degree Ahmedabad, Bangalore Roles & Responsibilities RTL programming (Verilog/System Verilog or VHDL). Knowledge of complete FPGA Design Development flow. Hands-on with FPGA Development Tools (Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc.). Functional verification using Verilog/System Verilog or VHDL. RTL Code Optimization to meet timings and fit on-chip resources. Support all phases of FPGA based product development activities. System Architecture Design. Testing and troubleshooting of hardware. Skills Requirements BE/B.Tech in Electronics/Electronics & Communication from a recognized university with a good academic record. ME/M.Tech in Electronics/VLSI Design from a recognized university with a good academic record. Experience with Verilog/SystemVerilog or VHDL for design and verification. In-depth understanding of FPGA design flow/methodology, IP integration, and design collateral. Should be able to develop the small blocks of IP from scratch and do basic functional verification. Should be familiar with protocols like SPI, I2C, UART and AXI. Understanding of standard/specification/application for IP design or system design. Knowledge of Altera Quartus II Tool, Questasim, Modelsim. Knowledge of Xilinx tools like ISE, and Vivado. Knowledge of Microsemi tools like libero. Knowledge of USB, Ethernet, and external memories such as DDR, QDR RAM and QSPI-NOR based Flash. Personal Competency Self-motivated to learn and contribute. Ability to work effectively with global teams. Able and willing to work in a team-oriented, collaborative environment. A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment. Proven analytical and creative problem-solving abilities. Passionate about writing clean and neat code that adheres to coding guidelines. Apply Now Related Job Openings Embedded Domain Embedded Software Engineer(Experienced) Min 3 - 7 Years of Experience Ahmedabad, Bangalore Read more details Embedded Domain Embedded Software Engineer(Fresher) Min 0 - 3 Years of Experience Ahmedabad, Bangalore Read more details Embedded Domain RTL/FPGA Design Engineer(Experienced) Min 3 - 7 Years of Experience Ahmedabad, Bangalore Read more details