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3.0 - 7.0 years
7 - 11 Lacs
hyderabad
Work from Office
We are seeking a highly skilled and experienced Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in chip-level and block-level physical design, timing closure, and signoff processes. This role requires proficiency in industry-standard tools and scripting, along with a strong understanding of design constraints and methodologies. Key Responsibilities: Perform chip-level floorplanning, partitioning, timing budget generation, and power planning.Execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation.Handle block-level implementation from netlist to GDSII.Drive timing closure for high-frequency blocks and manage blocks with high instance counts (1M+).Ensure signoff closure for timing (including SI and OCV), power, IR drop, and physical verification.Apply signal integrity (SI) prevention and fixing methodologies.Conduct layout edits and physical design optimizations.Automate design tasks and manage UNIX-based environments. Primary Skills: Chip-level and block-level physical design expertise.Hands-on experience with Synopsys ICC and PrimeTime.Proficient in signoff closure for timing, power, IR, and physical verification.Strong understanding of SI and OCV impacts and mitigation strategies.Experience with high-frequency designs and large instance count blocks.Proficient in layout editing techniques. Secondary Skills: Familiarity with Mentor Olympus and Atoptech toolsets.Experience in design automation.Proficiency in UNIX systems.Scripting knowledge in Tcl and/or PERL. Educational Qualification: Bachelors or Masters degree in Electrical Engineering, Electronics, VLSI, or a related field.
Posted Date not available
3.0 - 7.0 years
7 - 11 Lacs
hyderabad
Work from Office
We are seeking a highly skilled and experienced Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in chip-level and block-level physical design, timing closure, and signoff processes. This role requires proficiency in industry-standard tools and scripting, along with a strong understanding of design constraints and methodologies. Key Responsibilities: Perform chip-level floorplanning, partitioning, timing budget generation, and power planning.Execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation.Handle block-level implementation from netlist to GDSII.Drive timing closure for high-frequency blocks and manage blocks with high instance counts (1M+).Ensure signoff closure for timing (including SI and OCV), power, IR drop, and physical verification.Apply signal integrity (SI) prevention and fixing methodologies.Conduct layout edits and physical design optimizations.Automate design tasks and manage UNIX-based environments. Primary Skills: Chip-level and block-level physical design expertise.Hands-on experience with Synopsys ICC and PrimeTime.Proficient in signoff closure for timing, power, IR, and physical verification.Strong understanding of SI and OCV impacts and mitigation strategies.Experience with high-frequency designs and large instance count blocks.Proficient in layout editing techniques. Secondary Skills: Familiarity with Mentor Olympus and Atoptech toolsets.Experience in design automation.Proficiency in UNIX systems.Scripting knowledge in Tcl and/or PERL. Educational Qualification: Bachelors or Masters degree in Electrical Engineering, Electronics, VLSI, or a related field.
Posted Date not available
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