Staff Engineer, Emulation Based Power Analysis and Methodolgy Engineer

2 - 4 years

7 - 11 Lacs

Posted:18 hours ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

As part of the power methodology team, the Emulation-Based Power Analysis and Methodology Engineer will be responsible for developing and driving emulation-based power analysis strategies using RLE (Register-Level Emulation) and GLE (Gate-Level Emulation) techniques. This role focuses on building accurate, scalable flows that integrate power estimation with functional emulation to provide actionable insights on real-use power behavior across complex SoCs and IPs.

Responsibilities:

  • Develop and maintain power analysis methodologies demonstrating RLE and GLE platforms.
  • Collaborate with design and emulation teams to define use cases and collect realistic activity traces.
  • Automate power estimation workflows using SAIF/VCD generation from emulation runs.
  • Analyze multifaceted power consumption patterns under real-world workloads and use models.
  • Correlate emulation-based power data with RTL and gate-level power results to validate accuracy.
  • Build dashboards or scripts to visualize power hotspots and behavioral anomalies.
  • Work closely with architecture, DV, and software teams to align on performance and power validation goals.
  • Support deployment of the flow across global teams and train design teams on standard methodologies.

Required Skills and Experience :

  • proven experience in power analysis and emulation methodologies for ASIC or SoC design.
  • Hands-on experience with RLE and/or GLE platforms (e.g., Synopsys ZeBu, Cadence Palladium, Mentor Veloce).
  • Solid understanding of power estimation concepts, including multifaceted, static, and leakage power.
  • Experience in working with switching activity data (SAIF, VCD, FSDB).
  • Strong scripting and automation skills (Python, Perl, TCL, Bash).
  • Familiarity with power analysis tools like Synopsys PrimePower, PowerArtist, or Voltus.
  • Good knowledge of RTL/gate-level design, SoC architecture, and power-aware design techniques.

Nice To Have Skills and Experience :

  • Experience in correlating power between emulation, RTL, and silicon data.
  • Exposure to activity compression techniques and cycle-accurate modeling.
  • Familiarity with UPF/CPF-based power intent specification.
  • Prior experience with low-power design flows in mobile, automotive, or AI/ML SoCs.
  • Contribution to internal methodologies or EDA tool evaluations in emulation environments.

In Return:

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!
  • Partner and dedication towards or customers
  • Collaborate and communication
  • Originality and resourcefulness
  • Team and personal development
  • Impact and influence
  • Deliver on your promises

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ARM Embedded Technologies logo
ARM Embedded Technologies

Technology / Embedded Systems

San Jose

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