Staff Engineer, ASIC Development Engineering

Western Digital

5 - 9 years

20 - 25 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

automation asic backend chip design analog mixed signal debugging signal integrity physical design python

Work Mode

Work from Office

Job Type

Full Time

Job Description

We are seeking a highly skilled High-speed SERDES IO PHY Layout designer with 5 - 9 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, Automated PnR and a passion for solving challenging technical problems.

Key Responsibilities:

Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability.
Collaborate with design engineers to understand design requirements and translate them into precise layouts.
Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently.
Work experience of block PnR to closely interact with physical design team ensuring area/timing/backend compatibility of custom blocks into the overall chip design.
Identify and resolve layout-related issues, providing creative solutions to meet design specifications.
Conduct layout reviews and provide technical feedback to improve layout practices and methodologies.
Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes.
Qualifications

Bachelor s or Master s degree in Electrical Engineering, Electronics, or a related field.
5-10 years of experience in IO/Analog mixed-signal IC layout design and block level PnR
Proficiency in layout

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