Senior Rtl Design Engineer

ThunderSoft

9 - 14 years

20 - 32 Lacs

hyderabad bengaluru

Posted:None| Platform:

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Skills Required

cdc spyglass lint asic design rtl design asic synthesis rtl coding

Work Mode

Work from Office

Job Type

Full Time

Job Description

Greetings from ||Thundersoft||

Key Responsibilities:

Define and develop micro-architecture for complex digital blocks and/or SoC subsystems.
Develop synthesizable RTL using Verilog/SystemVerilog for new designs and enhancements.
Own end-to-end design tasks including coding, linting, CDC, SDC generation, and synthesis.
Perform RTL integration of IP blocks and subsystems into the top-level SoC.
Collaborate with verification, DV, and validation teams to drive high-quality designs.
Work with the physical design team to address timing, area, and power goals.
Contribute to design documentation, design reviews, and support silicon bring-up.
Lead or mentor junior team members as needed.
Interface with cross-functional teams including software, DFT, and systems architecture.

Required Qualifications:

Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in ASIC RTL design and development.
Expert in RTL coding (Verilog/SystemVerilog) and digital design principles.
Strong knowledge of SoC architecture, bus protocols (AXI, AHB, APB), and memory subsystems.
Experience with synthesis, timing constraints (SDC), and understanding of STA.
Proficient in tools such as Synopsys Design Compiler, VCS, Spyglass, etc.
Deep understanding of low-power design techniques, clock gating, power domains (UPF).
Familiarity with simulation and debugging tools.

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