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Senior Physical Design Engineer

Senior Physical Design Engineer

Truechip

5 - 10 years

0 Lacs

hyderabad telangana india

Posted:17 hours ago| Platform: Foundit logo

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Skills Required

dc cts ocv pt clock tree methodology lvs ir drop calibre innovus synthesis mmmc formal verification pd flow from netlist to gds genus si xtalk isolation cells floorplanning placement optimization em eco steps icc power planning clock skewing primetime redhawk multi power designs drc timing level shifters ptsi

Work Mode

On-site

Job Type

Full Time

Job Description

Senior Physical Design Engineer Physical Design >> Senior Physical Design Engineer

Post

Senior Physical Design Engineer

Required Experience

5 to 10 YearsLocation:Delhi NCR, Bangalore, HyderabadOpenings8-10EducationBE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication)Physical Design Engineerknowledge of PD Flow from netlist to GDS (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI)Good idea about OCV/MMMC and multi power designs (Level shifters, Isolation cells etc)Should have worked extensively on XTalk/SI/EMKnowledge about CTS, Clock tree methodology and clock skewing.Tool specific knowledge: ICC, innovus, primetime, DC, Genus depending on the backgroundKnowledge of DRC/LVS, IR Drop, Formal Verification and Synthesis.Job would require complete ownership from netlist to GDS for blocks.Should have worked on 28nm and lower technologies.Tools : ICC or Innovus for PnR , Encounter for FloorPlan , Redhawk for IR Drop, PT/PTSI , CalibreActivities : Physical design of Hard Macros/Partitions. gate-level- Netlist to GDS, technologies varying from 28nm to 7nm .

PD Activities Involve

Hard Macro floorplan/IR Drop/placement/CTS/Routing/Timing Optimization/Timing Closure/DRC/LVS

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Senior Physical Design Engineer