7.0 - 12.0 years

9 - 13 Lacs

bengaluru

Work from Office

Part of the global PCIe/CXL Center of Excellent (CoE) team, developing the latest & state of the art PCIe/CXL solution for next generation FPGA in the latest process technology node. Develops logic/RTL design and simulation for IP/SoC design & integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of PCIe/CXL architecture and microarchitecture features of the block being designed. Works with IP providers to integrate and validate IPs at the SoC level. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Drives quality assurance compliance for smooth IP/SoC handoff. Qualifications: Bachelor s degree in electrical/computer engineering or related field and 7+ years of experience Or a master s degree in electrical/computer engineering or related field and 6+ years of experience. Experience in micro-architecture (clocking, reset, power, etc) definition & debug. Good knowledge of PCIe/CXL or high-speed serial interface protocol, such as USB or Ethernet. 5+ years of RTL coding and/or IP integration experience into SoC design. Experience in design related tools such as LINT, CDC, PT-STA, Fishtail, Power UPF etc & design concept such as data flow, algorithm state machine, finite state machines, and timing charts. Knowledge on FPGA background would be a plus. Highly motivated individual, team player with good communication skill.

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Staff Design Engineer Evnek

10.0 - 15.0 years

6 - 9 Lacs

bengaluru

Work from Office

Job Role: Staff DesignEngineer Experience: 10+yrs Location: Bengaluru Notice Period: 30days max Role Summary We are seeking an experienced Design Engineer to join our team andcontribute to the RTL design and development of the signal processingpath for Aevaadvanced 4-D Lidar processing chip. In this role, you willdesign, implement, and integrate key sub-components into both ASIC and FPGAplatforms, ensuring performance, efficiency, and robustness. Key Responsibilities Design and develop custom components for the digital signal processing pipeline, including filters, FFTs, control logic, and related modules. Create micro-architecture specifications, write SystemVerilog RTL code, and perform testing and validation for Aeva-specific components. Integrate advanced features for functional safety, reliability, and robustness. Deliver high-performance, low-power, and scalable designs that meet stringent quality standards. Collaborate with architects, design engineers, verification engineers, and system software teams to ensure SoC functional, performance, and power objectives are achieved. Qualifications 10+ years of experience designing DSP architectures, algorithms, and signal processing functionalities in ASICs and/or FPGAs. Proven ability to meet high-performance and low-power design targets. Proficiency in SystemVerilog RTL coding. Hands-on experience with AMBA protocols . Strong problem-solving skills and a passion for implementing innovative processes and methodologies. Preferred Skills Experience with Matlab, NumPy, C, and/or C++ . Knowledge of LPDDR, Ethernet, MIPI, and high-speed SerDes . FPGA design experience and pre-silicon validation using emulation platforms (e.g., Cadence Palladium, Mentor Veloce, Synopsys Zebu). Post-silicon bring-up and validation expertise. Experience in diagnostics firmware development and validation.

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