Physical Design Engineers

Mirafra

2 - 5 years

7 - 11 Lacs

noida

Posted:1 day ago| Platform:

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Skills Required

python node pnr perl tcl sta physical design c++ cts static timing analysis device drivers timing analysis floorplan routing floor planning rtos drc timing closure embedded systems embedded c power management placement

Work Mode

Work from Office

Job Type

Full Time

Job Description

We are looking for bright Physical Design Engineer with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering High performance design, flows for high performance SoCs in sub-10nm process for mobile space.

Job Requirement:

2-5 years hands-on experience of different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure.
Well versed with high frequency design & advanced tech node implementation
In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience.
In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation.
Well versed with tackling high placement density/congestion bottlenecks.
In depth knowledge of PnR tool knobs/recipes for PPA optimization.
Experience in automation using Perl/Python and tcl.
Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

Experience (years) : 3+ Year

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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