Posted:15 hours ago|
Platform:
On-site
Full Time
Experience : 7-10 years
Location : Hyderabad
The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc . The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc.
Full Chip Floorplan:
Interested,please drop your updated resume to janagaradha.n@acldigital.com
ACL Digital
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