Middleware Engineer

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Build a high-performance, multi-transport communication stack ,

Ethernet, TCP/IP) with a clean transport abstraction and PDU routing under real-time constraints. You will engineer throughput/latency/jitter outcomes, ensure determinism and back-pressure handling, and provide instrumentation and testability across SIL/HIL.

Key Responsibilities:

COM layer

IPv4/IPv6, UDP/TCP;

3. Engineer buffering strategies (ring buffers, memory pools), zero-copy paths where

feasible, and QoS/back-pressure for deterministic behavior.

4. Instrument the stack with counters and timestamps; analyze traces

Wireshark and Vector CANoe/CANalyzer

5. Deliver measurable KPIs (throughput, one-way latency, jitter) under varying bus loads and failure scenarios (bus-off, link flap).

6. Implement robust error paths: timeouts, retransmissions, reconnection, bus-off recovery, and graceful degradation.

7. Develop unit/integration tests for SIL and HIL; add performance benches and golden datasets; integrate with GitLab CI.

8. Document APIs, routing tables, configuration knobs, and developer samples; support consumers (Diagnostics/Services).

9. Collaborate with Platform (HAL/RTD) on DMA/interrupt policies and

with Diagnostics on DoIP/UDS data paths.

Required Skills & Experience:

embedded

Vector CANoe/CANalyzer and Wireshark

lwIP/embedded TCP/IP

DMA-driven I/O

AVTP (IEEE 1722)

6. Comfort with lab work (probes, link impairment), performance tuning, and automated test harnesses.

ECE/EE/CS