High-Speed Analog Layout Engineer - Staff

• Collaborating with a team of experienced layout engineers to deliver optimized, reliable, and manufacturable designs.
• Utilizing advanced CAD tools (Custom Designer, Cadence Virtuoso, Calibre, ICV, STAR-RXCT) for layout creation, verification, and debugging.
• Executing deep submicron layout techniques, including floor-planning, ESD/latchup mitigation, and process technology adaptation.
• Implementing and verifying layout flows such as LEF generation, top-level verification, DRC/LVS/LPE, and power routing with EM/IR considerations.
• Providing technical leadership through knowledge sharing, status updates, and networking with senior internal/external stakeholders.
• Applying scripting skills for layout automation to enhance productivity and reduce manual efforts.

The Impact You Will Have:

• Delivering high-quality analog and mixed-signal IP layouts that enable next-generation silicon innovation.
• Elevating the performance and reliability of Synopsys IP portfolio through advanced layout techniques and verification processes.
• Driving successful tape-outs and product launches by ensuring robust design flows and manufacturability.
• Contributing to the technical advancement of the team with your expertise in deep submicron effects and process technology.
• Championing best practices in ESD/latchup mitigation, verification, and design for manufacturability (DFM).
• Fostering a collaborative culture by mentoring peers and sharing insights across cross-functional teams.
• Accelerating project timelines through layout automation and process optimization.

What You ll Need:

• BTech/MTech in Electronics or Electrical Engineering.
• 6+ years of hands-on experience in analog/mixed-signal IP layout and verification for high-speed analog circuits.
• Advanced proficiency with CAD tools such as Custom Designer, Cadence Virtuoso, Calibre, ICV, and STAR-RXCT.
• Solid understanding of deep submicron effects, CMOS/FinFET process technologies, and advanced floor-planning techniques.
• Experience in layout design flow: LEF generation, DRC/LVS/LPE verification, power routing, EM/IR considerations, and DFM.
• Strong analytical, debugging, and troubleshooting skills; scripting experience for layout automation is a plus.