50 Hardware Architecture Jobs - Page 2

As a software engineer at Google, you will play a crucial role in developing cutting-edge technologies that revolutionize how billions of users connect, explore, and engage with information globally. The projects you undertake will have a significant impact on advancing Google's capabilities beyond traditional web search, requiring expertise in various domains such as information retrieval, distributed computing, system design, networking, security, artificial intelligence, and more. Your responsibilities will involve writing and testing code for product or system development, as well as participating in design reviews to evaluate different technologies alongside your peers and stakeholders. You will also be expected to review code authored by fellow developers, ensuring adherence to best practices and providing constructive feedback for improvement. Moreover, you will contribute to enhancing existing documentation and educational materials, tailoring the content to reflect updates in products or programs based on user feedback. In the event of product or system issues, you will be responsible for triaging, debugging, and resolving them by analyzing their sources and assessing the impact on hardware, network, or service operations. Ideal candidates for this role should hold a Bachelor's degree or its equivalent, possess at least 5 years of experience in software development across various programming languages, and have 3 years of experience in testing, maintaining, or launching software products. Additionally, candidates should demonstrate proficiency in software design and architecture, with a minimum of 1 year of relevant experience. Preferred qualifications include a Master's degree or PhD in Computer Science or a related technical field, along with 5 years of experience in data structures and algorithms. Experience in a technical leadership role, developing accessible technologies, working with the Search or KE stack, and building ML models will be advantageous. Joining the Google Search team presents an exciting opportunity to redefine the search experience for users worldwide. By tackling complex engineering challenges and expanding infrastructure while prioritizing accessibility and usability, you will contribute to delivering a universally beneficial search platform relied upon by billions. Your role will involve continuous learning, adaptability, and leadership in solving diverse problems across the full technology stack, driving innovation and progress within the organization.,

As a software engineer at Google, you will have the opportunity to work on next-generation technologies that impact billions of users worldwide. Your role will involve developing innovative solutions that go beyond web search, requiring you to handle information at massive scales. We are seeking individuals with diverse expertise in areas such as information retrieval, distributed computing, system design, networking, security, artificial intelligence, UI design, and mobile technologies. Our engineers play a crucial role in building and evolving Google's infrastructure, enabling the seamless operation of our diverse product portfolio. From maintaining data centers to creating cutting-edge platforms, the Technical Infrastructure team is at the core of Google's success. As a software engineer, you will have the chance to work on critical projects that address Google's evolving needs, with the flexibility to transition between teams and projects. Key Qualifications: - Bachelor's degree or equivalent practical experience. - 2 years of experience in software development using C++. - Proficiency in data structures or algorithms in academic or industry settings. Preferred Qualifications: - Master's degree or PhD in Computer Science or related field. - 2 years of experience in building large-scale infrastructure, distributed systems, or networks. - Experience in developing accessible technologies. In this role, your responsibilities will include writing code for product or system development, participating in design reviews, and providing feedback on code quality. You will also contribute to documentation and educational content, ensuring alignment with product updates and user feedback. Additionally, you will be responsible for triaging and resolving product or system issues by analyzing their sources and impact on hardware, network, or service operations. Join us at Google Cloud and be part of a team that accelerates digital transformation for organizations worldwide, offering enterprise-grade solutions powered by Google's advanced technology. With customers in over 200 countries, Google Cloud is a trusted partner for growth and problem-solving.,

You are an experienced Service Line Specialist with 20 to 24 years of experience in Hardware Architecture. Your expertise lies in Value Analysis & Value Engineering and Product Lifecycle Management. In this role, you will be responsible for leading technical projects, providing strategic insights, and ensuring the successful implementation of hardware solutions to achieve business objectives. Your responsibilities will include managing customer projects, coordinating tasks across various functional groups, and driving delivery with offshore teams. You have managed medium to large teams of approximately 30+ hardware engineers and possess skills in full hardware development to production cycles. Your deep expertise in analog electronics for competitive products requiring low power high accuracy interfaces to field sensors and transducers will be valuable. You are familiar with industry standards for IO and industrial standard communications, as well as 32-bit/64-bit processor-based design and microcontroller-based design. Your exposure to Memory devices and working experience with global compliance standards for EMI/EMC functional safety will be beneficial. You are capable of hands-on design and conducting design reviews of schematics and PCB testing. Your experience in reverse engineering analysis, familiarity with industry-wide tools for schematics and PCB, and ability to guide teams in circuit-level analysis and simulations are essential. Certifications Required: - Certified Hardware Architect - Certified Product Lifecycle Manager,

Job Specs : - Expertise in the x86 BIOS / UEFI FSP / coreboot development - Expertise with x86 CPU/APU architectures and associated compilation tools - Expertise in C programming - Expertise with platform bring-up - Expertise with standard protocols like PCIe, SPI, eSPI, ACPI, SMM - Expertise with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms. - Expertise on working with Intel FSP package source code and understanding of coreboot & FSP boot flow - Expertise with different coreboot payloads like edk2, SeaBios, Tianocore etc - Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required - Good coreboot upstreaming exposure - Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff - Understanding of coreboot & FSP build tools and build processes - Good understanding of UEFI framework concepts to port UEFI code to FSP - Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. - Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. - Good understanding of x86-64 architecture from BIOS developer's perspective. - Good understanding of UEFI BIOS Boot flow. - Basic understanding of Linux Kernel like software development concepts (Kconfig).

Experience in System Architecture, Hardware Circuit Design, OrCAD Capture. Expertise in High Power/Power Electronics (AC/DC), High-Speed/RF Design. Skilled in hardware architecture, component selection, PCB verification (Allegro 16.3+), Gerber tools.

Manage IT infrastructure (devices, enterprise apps, network) with focus on cybersecurity. Oversee vendor relations, procurement, and tech support. Min. 2-4 yrs exp, network expertise (switches, routers, LAN), leadership, and excellent comm required Perks and benefits Health insurance Paid sick time Provident Fund

Job Title : Android HAL Developer Experience : 3-6 years Location : Hyderabad Education : B.Tech/M.Tech in ECE, CS, EEE Notice Period : Immediate to 3 months Key Responsibilities : - Design, develop, and maintain Android Hardware Abstraction Layers (HALs) for various hardware components (camera, audio, display, etc.). - Port HALs to different Android platforms and SoCs. - Optimize HAL performance and power consumption. - Work closely with hardware and software teams to ensure seamless integration. - Troubleshoot and resolve HAL-related issues. - Stay updated with the latest Android HAL development practices and industry trends. Required Skills : - Strong proficiency in C and C++ programming languages. - In-depth understanding of Android architecture and HAL concepts. - Experience with Android kernel and device driver development. - Knowledge of hardware interfaces (I2C, SPI, MIPI, USB). - Familiarity with Android frameworks (Binder IPC, HAL, HIDL). - Experience with debugging tools and techniques. - Good problem-solving and analytical skills. - Strong communication and teamwork abilities. Preferred Skills : - Experience with Android framework development. - Knowledge of Android security and performance optimization techniques. - Experience with scripting languages (Python, Shell). - Familiarity with real-time operating systems (RTOS).

Expertise in the x86 BIOS / UEFI FSP / coreboot development. Expertise with x86 CPU/APU architectures and associated compilation tools. Expertise in C programming. Expertise with platform bring-up. Expertise with standard protocols like PCIe, SPI, eSPI, ACPI, SMM. Expertise with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms.. Expertise on working with Intel FSP package source code and understanding of coreboot & FSP boot flow. Expertise with different coreboot payloads like edk2, SeaBios, Tianocore etc. Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required. Good coreboot upstreaming exposure. Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff. Understanding of coreboot & FSP build tools and build processes. Good understanding of UEFI framework concepts to port UEFI code to FSP. Working knowledge of Git for code reviews, source code management, and BIOS releases to QA.. Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements.. Good understanding of x86-64 architecture from BIOS developer's perspective.. Good understanding of UEFI BIOS Boot flow.. Basic understanding of Linux Kernel like software development concepts (Kconfig).. Location-Delhi NCR,Bangalore,Chennai,Pune,Kolkata,Ahmedabad,Mumbai,Hyderabad

Job Specs : - Expertise in the x86 BIOS / UEFI FSP / coreboot development - Expertise with x86 CPU/APU architectures and associated compilation tools - Expertise in C programming - Expertise with platform bring-up - Expertise with standard protocols like PCIe, SPI, eSPI, ACPI, SMM - Expertise with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms. - Expertise on working with Intel FSP package source code and understanding of coreboot & FSP boot flow - Expertise with different coreboot payloads like edk2, SeaBios, Tianocore etc - Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required - Good coreboot upstreaming exposure - Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff - Understanding of coreboot & FSP build tools and build processes - Good understanding of UEFI framework concepts to port UEFI code to FSP - Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. - Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. - Good understanding of x86-64 architecture from BIOS developer's perspective. - Good understanding of UEFI BIOS Boot flow. - Basic understanding of Linux Kernel like software development concepts (Kconfig).

Hardware Architecture & Design, Lead PCB Development, Provide Technical Leadership,5. Documentation & Process, high-speed digital design, signal/power integrity analysis, and EMC mitigation

Hardware Architecture & Design, Lead PCB Development, Provide Technical Leadership,5. Documentation & Process, high-speed digital design, signal/power integrity analysis, and EMC mitigation

You will be responsible for SVT (System Verification Test) for one or more z/OS BCP components. You will plan, code, and execute end-to-end tests involving Z hardware and the z/OS operating system in both customer-like and stress-workload environments. Developing new test scenarios to support upcoming enhancements in z/OS BCP components. Write end-to-end test plans, with appropriate reviews along the way. Test execution and logging your test activities and results on an ongoing basis. Work with development teams to find defects, attempt to reproduce them, and verify fixes. Reproduce issues found by customers. Collect necessary documentation (dumps, logs, slip traps, etc) for diagnosing defects. Open defects/issues providing clear and complete information about symptoms, associated documentation and any analysis and repro attempts. Write and enhance code for test cases as needed, automating as much as possible. Maintain and enhance automated regression buckets. Track test status and clearly communicate status and blocking issues to peers, development and management. Maintain your test environment in coordination with other teams and lead System Programmers. This includes keeping software levels current, configuring z/OS and the hardware for test scenarios, and monitoring the health of the systems. Required education Bachelor's Degree Required technical and professional expertise Knowledge of Z Hardware Architecture and general z/OS facilities. Understanding of Basic System Programming concepts. Experience with coding and debugging. Experienced in writing Python and/or REXX code. Familiar with writing and debugging PL/X, Assembler and/or zTT code. ISPF navigation, editor, data set management (allocating, copying, etc) SDSF job management. Ability to monitor the health of a system by interpreting syslog messages, RMF reports, SMF data and other metrics. Ability to recognize abends and dumps. Ability to navigate HMC to IPL/RESET systems and check system status as appropriate. Understanding of corporate tools (Slack, Teams, Outlook etc.) Preferred technical and professional experience Unix/Linux system administration and shell scripting. IPCS and Dump Reading. Writing blogs, papers, and technical documents. Opportunities for innovation/patent.

Job Title: Hardware Design Engineer - AUVs Location: Kolkata, onsite Employment Type: Full-Time Team: Hardware Engineering JD & Form Below: https://docs.google.com/document/d/1vkUg42Nf2XbjXp0Ia60ZX-V_ROyeAyA4R8JO0CvL55U/edit?usp=sharing

What You Will Do: You will bring your unique talents to a team that develops Cisco's cutting-edge routing technology, widely regarded as the transport medium of choice for mission-critical networks in large enterprises. As a Software Technical Leader , you will: Design, Develop and integrate products deployed by leading service providers worldwide. Collaborate with a vibrant, BU-wide technical community to exchange ideas and innovate on next-generation technology. Explore opportunities for personal growth while mentoring colleagues and working on cutting-edge technologies. As a key member of this team, you will: Work alongside seasoned engineers to architect, design, and develop some of the world's largest service provider routers, web centres, and enterprises. Contribute to the evolution of these systems to support exciting new customer business paradigms. Interact and collaborate with some of the finest talent in the industry, making work both fun and challenging. Engage with other groups such as Product Management, Marketing, Sales, Customer Support, and Advanced Services. Who You Are: You possess: In-depth knowledge of C and a solid understanding of Python. Extensive experience in a Unix/Linux-based development environment. Excellent coding, automation, and debugging skills. Strong teamwork and communication skills. Familiarity with hardware architectures such as PCI, PCIe, DMA, I2C, SPI , NPUs/DPUs and processors like x86, AMD, and ARM . Experience with board bring up is a plus. Experience with emerging technologies such as AI/ML and cloud computing is a plus. Experience and Qualifications: Experience: 12 to 15 years in embedded firmware development. Education: BE/B.Tech/ME/M.Tech/MS in CS/EE/IT/ECE, MCA, or similar education. Proven ability to derive design and code based on technical standards and write comprehensive, focused design documents. Experience in developing software/firmware for networking equipment. Excellent knowledge of software architecture and system design.

Education : B.Tech/M.Tech in ECE, CS, EEE Notice Period : Immediate to 3 months Key Responsibilities : - Design, develop, and maintain Android Hardware Abstraction Layers (HALs) for various hardware components (camera, audio, display, etc.). - Port HALs to different Android platforms and SoCs. - Optimize HAL performance and power consumption. - Work closely with hardware and software teams to ensure seamless integration. - Troubleshoot and resolve HAL-related issues. - Stay updated with the latest Android HAL development practices and industry trends. Required Skills : - Strong proficiency in C and C++ programming languages. - In-depth understanding of Android architecture and HAL concepts. - Experience with Android kernel and device driver development. - Knowledge of hardware interfaces (I2C, SPI, MIPI, USB). - Familiarity with Android frameworks (Binder IPC, HAL, HIDL). - Experience with debugging tools and techniques. - Good problem-solving and analytical skills. - Strong communication and teamwork abilities. Preferred Skills : - Experience with Android framework development. - Knowledge of Android security and performance optimization techniques. - Experience with scripting languages (Python, Shell). - Familiarity with real-time operating systems (RTOS). Keywords HIDL,RTOS,Hardware Abstraction Layer,Android,Hardware Architecture,Mobile App Designing,Mobile App Integration,Mobile Architecture,SoC,Kernel,Device Driver,C++*

Work Location : Bangalore, Belgrade, Penang, New York Work Expertise : 5 - 15 years Job Specs : - Expertise in the x86 BIOS / UEFI FSP / coreboot development - Expertise with x86 CPU/APU architectures and associated compilation tools - Expertise in C programming - Expertise with platform bring-up - Expertise with standard protocols like PCIe, SPI, eSPI, ACPI, SMM - Expertise with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms. - Expertise on working with Intel FSP package source code and understanding of coreboot & FSP boot flow - Expertise with different coreboot payloads like edk2, SeaBios, Tianocore etc - Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required - Good coreboot upstreaming exposure - Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff - Understanding of coreboot & FSP build tools and build processes - Good understanding of UEFI framework concepts to port UEFI code to FSP - Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. - Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. - Good understanding of x86-64 architecture from BIOS developer's perspective. - Good understanding of UEFI BIOS Boot flow. - Basic understanding of Linux Kernel like software development concepts (Kconfig).

We are seeking a competent and enthusiastic Senior Hardware Design Engineer with expertise in Altium Designer and a strong background in hardware design and testing for automotive applications in the Electric Vehicle (EV) domain. Role Overview: As a Senior Hardware Design Engineer, you will play a critical role in designing, executing, and supporting Battery Management Systems (BMS), Vehicle Control Units (VCU), and Motor Control Units (MCU) for both low-voltage and high-voltage applications. You will work in a dynamic environment, collaborating across teams to drive innovation, reliability, and performance in our products. The ideal candidate is highly motivated, detail-oriented, and solution-driven, with a relentless focus on delivering high-quality, on-time results. This role requires someone who does not limit themselves by defined responsibilities but instead takes ownership to ensure the success of the product. Key Responsibilities: Design and develop analog, digital, and mixed-signal circuits, including motor control systems, power supplies, and embedded hardware Create circuit schematics, perform simulations (PSPICE, LTSPICE), and oversee PCB layouts Optimize hardware designs for manufacturability, reliability, and regulatory compliance. Design and analyze DC/DC switch-mode power supplies (SMPS) and linear power supplies, including flyback, buck converters, linear regulators, and series pass regulators. Perform detailed component selection, including resistors, capacitors, diodes, transistors, MOSFETs, IGBTs, gate drivers, and overcurrent/overvoltage protection circuits. Ensure compliance with EMI/EMC regulations, troubleshoot and resolve electromagnetic interference issues. Conduct detailed electrical analysis, calculating currents and voltages across all circuit components. Prepare engineering documentation, including hardware design documents, test plans, and validation reports. Research and implement emerging technologies to drive innovation in power electronics and embedded hardware. Evaluate and recommend cost-effective, scalable technological alternatives for future product development. Apply thermal management techniques and electromagnetic compatibility (EMC) best practices in hardware design. Ensure strict adherence to safety standards and regulatory requirements throughout the development lifecycle. Demonstrate expertise in ISO 26262 functional safety standards, specifically ASIL C/ASIL D-compliant designs. Collaborate closely with cross-functional teams, including firmware, software, and system engineering, to ensure seamless product integration. Qualifications & Skills: BE/ B.Tech OR ME / MTech / MS in Electonics / Electrical / Instrumentation / Robotics, etc. 2+ years of hands-on experience in automotive hardware design and testing. Strong expertise in Altium Designer for schematic capture, PCB layout, and design reviews. In-depth knowledge of power electronics, battery management systems, and vehicle control architectures. Experience in EMI/EMC compliance, thermal management, and functional safety (ISO 26262 ASIL C/D). Proficiency in circuit simulation tools (PSPICE, LTSPICE) and hardware debugging techniques. Ability to analyze and optimize PCB layouts for signal integrity, power efficiency, and thermal performance. Strong problem-solving skills with the ability to troubleshoot hardware issues at both component and system levels. Passion for electric mobility and automotive innovation, with a proactive and ownership-driven mindset.

Minimum Qualifications: Experienced candidates (1 - 4 years) are welcome to apply with experience in the following area: Strong academic records (GPA 3.0 or 72% and better) Excellent programming skills in C/C++, Python Strong problem-solving skills Strong motivation and capabilities in learning new subjects especially in the field of artificial intelligence Knowledge of data-driven modelling Knowledge of computer and hardware architecture Effective interpersonal communications skill (written and verbal) Analytical, thorough, resourceful, and detail-oriented Self-motivated, hardworking, and flexible Preferred Qualifications: Basic understanding of machine learning, computer vision, and digital image processing algorithms and applications Advanced understanding of computer architecture Advanced understanding of data-driven modelling Excellent verbal, written, and presentation skills Ability to work effectively as part of a team Knowledge of OOP principles Knowledge of GPU Programming / Architecture is a bonus Minimum Education Required Masters/Bachelors Computer Engineering, Electrical Engineering or Engineering Science Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.

What You'll Be Doing : - In this position, you will expect to lead all block/chip level PD activities. - PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. - Work in collaboration with design team for addressing design challenges. - Help team members in debugging tool/design related issues. - Constantly look for improvement in RTL2GDS flow to improve PPA. - Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. - Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. Minimum Qualifications : - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. What We Need To See : - Strong experience in Physical Design. - Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. - Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. - Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. - Well versed with timing constraints, STA and timing closure. - Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. - Ability to multi-task and flexibility to work in global environment. - Good communication skills and strong motivation, Strong analytical & Problem solving skills. - Proficiency using Perl, Tcl, Make scripting is preferred. - Widely considered to be one of the technology worlds most desirable employers, offers highly competitive salaries and a comprehensive benefits package.

Work Location : Bangalore, Belgrade, Penang, New York Work Expertise : 5 - 15 years Job Specs : - Expertise in the x86 BIOS / UEFI FSP / coreboot development - Expertise with x86 CPU/APU architectures and associated compilation tools - Expertise in C programming - Expertise with platform bring-up - Expertise with standard protocols like PCIe, SPI, eSPI, ACPI, SMM - Expertise with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms. - Expertise on working with Intel FSP package source code and understanding of coreboot & FSP boot flow - Expertise with different coreboot payloads like edk2, SeaBios, Tianocore etc - Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required - Good coreboot upstreaming exposure - Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff - Understanding of coreboot & FSP build tools and build processes - Good understanding of UEFI framework concepts to port UEFI code to FSP - Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. - Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. - Good understanding of x86-64 architecture from BIOS developer's perspective. - Good understanding of UEFI BIOS Boot flow. - Basic understanding of Linux Kernel like software development concepts (Kconfig).

. Principal /Senior Staff /Staff Machine Learning Compiler Engineer Bangalore Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon . Principal /Senior Staff /Staff Machine Learning Compiler Engineer experience-5-20 years Responsibilities: Develop and maintain compilers specifically designed for optimizing ML models. This includes translating high-level ML model descriptions into efficient mapping to our hardware architecture, optimizing for performance metrics such as flop utilization, memory bandwidth, and memory capacity. - Skills Required: Deep understanding of ML compiler design and optimization techniques, proficiency in MLIR and programming languages like C/C++, in-depth knowledge of ML frameworks (PyTorch) and Python. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

. Principal /Senior Staff /Staff Machine Learning Compiler Engineer Bangalore Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon . Principal /Senior Staff /Staff Machine Learning Compiler Engineerexperience-5-20 yearsResponsibilities: Develop and maintain compilers specifically designed for optimizing ML models. Thisincludes translating high-level ML model descriptions into efficient mapping to our hardwarearchitecture, optimizing for performance metrics such as flop utilization, memory bandwidth, andmemory capacity.- Skills Required: Deep understanding of ML compiler design and optimization techniques, proficiencyin MLIR and programming languages like C/C++, in-depth knowledge of ML frameworks (PyTorch) andPython.Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"

What You'll Be Doing : - In this position, you will expect to lead all block/chip level PD activities. - PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. - Work in collaboration with design team for addressing design challenges. - Help team members in debugging tool/design related issues. - Constantly look for improvement in RTL2GDS flow to improve PPA. - Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. - Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. Minimum Qualifications : - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. What We Need To See : - Strong experience in Physical Design. - Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. - Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. - Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. - Well versed with timing constraints, STA and timing closure. - Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. - Ability to multi-task and flexibility to work in global environment. - Good communication skills and strong motivation, Strong analytical & Problem solving skills. - Proficiency using Perl, Tcl, Make scripting is preferred. - Widely considered to be one of the technology worlds most desirable employers, offers highly competitive salaries and a comprehensive benefits package. Require candidates with a minimum of 5 years of relevant experience

Part of execution-focused hardware team responsible for successful development and productization of in-house designed Vehicle Electronic Control Units. The selected candidate for this role must work with all internal stakeholders as well as external suppliers and partners to drive the product through its design, development, and test cycles as well as vehicle integration. The successful candidate must demonstrate a keen interest as well as broad technical skills and understanding of embedded electronic hardware control units in automotive domain. The main job responsibilities will include but not limited to: Conceptualize the HW architecture deduce High Level Block Diagram & define I/O configuration for the next generation Body Control Modules, Zonal Computers, High Performance Computers. Responsible for answering/participating customer RFI/RFQ, able to provide inputs/effort estimation with detailed task planning, customer queries related to hardware. Proficient in implementing design for Communication protocols like I2C, SPI, RS232, RS485, USB, CAN, CAN-FD, LIN, Ethernet Diagnostic communication protocols e.g., KWP2000, UDS Perform Component selection, design Schematic using 8bit / 16bit / 32bit micro controllers & Circuit Simulation using tool like: Pspice / LTspice etc. Carry out design with OPAMP, MOSFETs based circuits, digital and analog interfaces and Power Electronics (High Side Driver / Low side Driver selection, Motor Driver. Proficient with design of LDO, DC-DC convertor, PMIC etc. Worst-case Analysis & Design calculations, Component & Vehicle level HW testing/IO testing. EMI/EMC filter design, DV/PV (EMI/EMC) test plan creation, testing and result evaluation for designed Control Units. Field failure root cause analysis and resolution (Electromechanical/Discrete Analog), DFMEA. Work proactively with silicon vendor partners to drive the next gen design/ solutions. Proficient in Altium, Cadence & Mentor Graphics Tool chain for schematic design, BOM release & layout review. Ability to collaborate and work with global OEMs spread across different regions and time zones. Basic Qualifications : B.E/B.Tech or M.E/M.Tech in Electrical/Electronics, Telecommunication, or equivalent Engineering Experience in automotive embedded electronics designs or hardware/ architectural role. Knowledge of Automotive Verification & Validation Standards like CISPR, IEC etc. Experience in designing Automotive ECUs for e.g. Body Control Module, Door Control Module, Zonal Computers etc. Understanding of functions like Gateway, OTA, Digital Key etc Strong teamwork spirit, excellent oral and written communication skills. Preferred Qualifications: Experience in Vehicle Regulatory norms that could impact ECU design. Understanding of Board software/Bring up software. Knowledge of safety standards including ISO 26262, ASIL Compliance, and Cyber Security regulations would be a plus.

Job Specs : - Expertise in the x86 BIOS / UEFI FSP / coreboot development - Expertise with x86 CPU/APU architectures and associated compilation tools - Expertise in C programming - Expertise with platform bring-up - Expertise with standard protocols like PCIe, SPI, eSPI, ACPI, SMM - Expertise with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms. - Expertise on working with Intel FSP package source code and understanding of coreboot & FSP boot flow - Expertise with different coreboot payloads like edk2, SeaBios, Tianocore etc - Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required - Good coreboot upstreaming exposure - Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff - Understanding of coreboot & FSP build tools and build processes - Good understanding of UEFI framework concepts to port UEFI code to FSP - Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. - Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. - Good understanding of x86-64 architecture from BIOS developer's perspective. - Good understanding of UEFI BIOS Boot flow. - Basic understanding of Linux Kernel like software development concepts (Kconfig).