38 Functional Coverage Jobs - Page 2

As a Semiconductor Design Engineer 2 with 3-5 years of experience, based in Hyderabad, you will be responsible for fast spice (Prime sim/Fine sim/spectre) based verification. Your role will involve guiding and setting the direction for the verification effort within your areas of expertise in any project that the team undertakes. You should possess strong circuit understanding, block-level circuit simulation, and analysis capability. Additionally, you are expected to analyze the test modes, have basic DFT understanding, and provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs. Your responsibilities will include developing test ...

Job Description: We are looking for an experienced SoC DV Lead with a strong background in SoC verification and hands-on experience in writing C test cases for SoC-level DV. Key Responsibilities: Lead SoC DV activities from planning to closure Develop and debug C-based test cases for system-level verification Work closely with design, architecture, and firmware teams Perform coverage analysis and ensure comprehensive validation Guide and mentor junior DV engineers Key Skills: SoC-level design verification C programming for test development Debugging and problem-solving Exposure to UVM/SystemVerilog (preferred) Strong understanding of SoC architecture

As a Verification Engineer, you will be responsible for utilizing your 2+ years of experience in ASIC/FPGA verification to develop test plans and verification strategies that thoroughly and effectively validate requirements and specifications. Your expertise in developing SV + UVM based verification environment components, such as agents/UVCs, scoreboards, predictors/reference models, and creating tests using constrained random based test sequences will be essential for success in this role. Your role will also involve implementing functional coverage, identifying and resolving coverage gaps, and writing tests to ensure comprehensive verification. Additionally, you will have the opportunity ...

This is a verification-focused individual contributor's role within the DesignWare IP Verification R&D team at our Bangalore Design Center, India. As a part of this team, you will be responsible for implementing state-of-the-art Verification environments for the DesignWare family of synthesizable cores and executing Verification tasks for the IP cores. You will collaborate closely with the RTL design team and work alongside a global team of expert Verification Engineers. The domains you will be working on include USB, PCI Express, Ethernet, and AMBA. Your responsibilities in this role will encompass a variety of tasks such as Test planning, Test environment coding at both unit and system lev...

Description We are seeking a skilled Verification Engineer to join our team in India. The ideal candidate will have a strong background in digital design verification and will be responsible for ensuring the quality and reliability of our products through rigorous testing and analysis. Responsibilities Develop and implement verification plans and test cases for digital designs. Perform functional and performance verification using simulation and formal verification techniques. Collaborate with design engineers to understand specifications and requirements. Debug and analyze issues found during verification, providing feedback to design teams. Generate reports and documentation for verificati...

Job Description Summary Oracle HCM Tech (Integrations, Data Conversion , Reports, Fast Formulas , OIC(Optional)) + Functional Coverage Job Description Functional knowledge of Compensation and Equity area in Oracle is plus -HCM Techno-Functional Engineers / Integration Engineers with core expertise in HCM extract , HCM API integration , HDL imports . Added expertise in Mulesoft would be a highly desirable but not mandatory. Oracle HCM Tech (Integrations, Data Conversion , Reports, Fast Formulas, OIC(Optional)) + Functional Coverage. Hands-on expertise with Oracle HCM tools such as OTBI, BI Publisher, and HDL/SDL. Optional experience with Oracle Integration Cloud (OIC) is a strong advantage. S...

Application of Metric-driven Verification (MDV) and/or Formal Verification methodologies Developing and tracking of Verification plans Develop verification environments from scratch Create VIP Integration of VIP (Verification-IP) Measure and analyze regression results Continuous improvement of verification methods/tools/flows/processes together with EDA partners Requirement: 5 to 10 years of Experience in Digital RTL verification using System Verilog and UVM. Sound knowledge of constrained random verification, UVM/OVM Sound knowledge in System Verilog. Experience of developing functional coverage code, coverage analysis. Experience of developing verification environments from scratch is desi...

Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) Generate verification test plan, verification environment documentation and test environment usage documentation Define, develop, and verify complex UVM verification environments Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers, VIP team to accomplish tasks Identify design problems, possible corrective actions and/o...

Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) Generate verification test plan, verification environment documentation and test environment usage documentation Define, develop, and verify complex UVM verification environments Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers, VIP team to accomplish tasks Identify design problems, possible corrective actions and/o...

Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) Generate verification test plan, verification environment documentation and test environment usage documentation Define, develop, and verify complex UVM verification environments Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers, VIP team to accomplish tasks Identify design problems, possible corrective actions and/o...

Specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores. Perform verification tasks for IP cores, working closely with RTL designers. Drive ownership of critical areas of verification along with a team of talented verification engineers. Develop and implement advanced test plans and test environments at both unit and system levels. Code and debug test cases, implementing complex checkers and assertions. Extract and review functional coverage (FC) and code coverage metrics, ensuring quality metric goals are met. Manage regressions and contribute to the continuous improvement of verification strategies and test environments. Th...

What You'll Be Doing: Developing and reviewing verification plans for SERDES/PHY/Controller IPs. Creating and maintaining verification environments, with a preference for UVM. Conducting RTL, GLS, and co-simulations to ensure comprehensive coverage closure. Delivering high-quality RTL and simulation models to customers. Using third-party VIP for protocol verification and simulation bring-up of protocol subsystems. Supporting customers with IP integration, silicon bring-up, and debugging issues. Demonstrating Testchip+FPGA system demos to customers and at conferences. The Impact You Will Have: Ensuring the compliance and functionality of our interface IPs with industry protocols. Enhancing th...

Creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chip-to-chip, die-to-die, coherent, and non-coherent design topologies. Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Deb...