Design for Testability Engineer, Silicon

Role Overview: As a member of our dynamic team, you will contribute to the development of custom silicon solutions that drive the future of Google's direct-to-consumer products. Your role will be pivotal in innovating products that are globally cherished, influencing the next wave of hardware experiences to deliver exceptional performance, efficiency, and integration. You will work towards Google's mission of organizing the world's information and making it universally accessible and useful, synergizing the best of Google AI, Software, and Hardware to craft profoundly beneficial experiences. The team is dedicated to researching, designing, and advancing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to enhance people's lives through technology. Key Responsibilities: - Collaborate with a team dedicated to Design for Testing (DFT) verification - Generate patterns for testing and conduct Standard Delay Format (SDF) simulations - Perform Static Timing Analysis (STA) checks - Craft Pattern delivery using Automatic Test Pattern Generation (ATPG) - Engage in Silicon bring-up activities - Work on Yield, Vmin, or Return Materials/Merchandise Authorization (RMA) debug - Deliver debug patterns and conduct Silicon data analysis Qualifications Required: - Hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field - Possess at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test - Have familiarity with ATPG, Low Value (LV), Built-in self-test (BIST), or Joint Test Action Group (JTAG) tools and flow - Ideally, have experience with a programming language like Perl - Expertise in Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC), DFT timing, and Static Timing Analysis (STA) - Proficiency in performance design DFT techniques - Understanding of end-to-end flows in Design, Verification, DFT, and Partner Domains (PD) - Ability to scale DFT would be advantageous,