39 Coverage Analysis Jobs

Hiring DFT Lead (10–20 yrs) with expertise in ATPG, Scan/MBIST/JTAG, pattern validation, Synopsys/Cadence/Mentor tools, Perl/TCL scripting, and strong leadership skills. Required Candidate profile Experienced DFT Lead (10–20 yrs) skilled in ATPG, Scan/MBIST/JTAG, pattern validation, Synopsys/Cadence/Mentor tools, Perl/TCL scripting, debugging, and leadership.

About Iravan Iravan Technologies, headquartered in Pune, is a semiconductor design services company specializing in Mixed-Signal, Digital, and Formal Verification. We partner with leading companies across Storage, Networking, Aerospace, Automotive, Defense, and other critical industries to deliver advanced semiconductor solutions. Designation : AMS Verification Engineer Experience: M.Tech + 1 year of relevant industry experience in Analog Domain OR 2+ years of experience in AMS Verification Location: BLR/Pune/HYD Vacancies :03 JD Strong fundamentals in mixed-signal designs, including a thorough understanding of analog building blocks Writing and maintaining Analog Mixed Signal models, using ...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced SoC Verification professional, passionate about enabling next-generation technologies and delivering robust, high-quality silicon solutions. You thrive in collaborative and fast-paced environments, leveraging your technical expertise and leadership skills to...

Technical Lead - Design Verification Experience: 8+ Years Location: Bengaluru We are seeking a highly skilled and experienced Senior Design Verification Engineer to join our SoC/ASIC verification team in Bangalore. The ideal candidate will have a deep understanding of the verification lifecycle, from test planning to coverage closure, and be able to independently drive complex verification tasks for IP, subsystem, or full-chip level designs. Key Responsibilities: Develop and execute test plans for IP/subsystem/full-chip level verification. Build and maintain constrained-random and directed testbenches using SystemVerilog and UVM. Drive functional coverage closure and ensure high-quality tape...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. We are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world's most advanced technol...

Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test (DFT) methodologies, implementation, and verification to build best-in-class System on a Chip (SOC) and IP for data center applications. The role offers the opportunity to apply your expertise in Design for Testability (DFT) methodologies and IP/SOC implementation. You will leverage and further develop your understanding of Siemens/Synopsys DFT EDA tools and IEEE standards (1149, 1500, 1687). ASIC Implementation, DFT Engineer Responsibilities: Develop and implement DFT strategies for data center scale large/disaggregated SOCs, considering factors such as fault coverage, test time, and in-syste...

As a DFT Engineer in Bangalore, India with over 6 years of experience, your role will involve the following responsibilities: - In-depth knowledge and hands-on experience in scan insertion, ATPG, coverage analysis, and Transition delay test coverage analysis. - Analyzing design and proposing the best compression techniques. - Debugging and resolving DRC issues. - Collaborating with the front-end team to provide solutions and ensure DFT DRCs are fixed. - Generating high-quality manufacturing ATPG test patterns for SAF (stuck-at fault), transition fault (TDF), and Path Delay fault (PDF) models through the use of on-chip test compression techniques. - Working experience in Synopsis TetraMax/DFT...

Tech Lead : 8 to 15 Years Job Locations : Bangalore/Hyderabad/Ahmedabad/Chennai (WORK FROM OFFICE ONLY) (NO WORK FROM HOME OR REMOTE WORK) What We Offer : A Fortune 109 Employer Brand Best In Class Employee Welfare Practices Cutting Edge, Full Chip ODC Projects Higher Education Sponsorship in Top Notch Institutes Good Salary & Perks Job Description: Must have expertise in ASIC verification methodologies and ASIC design flow Experience working of SV and UVM methodology and knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR or similar is required, must have executed at-least 2 SoC Verification projects Experience in any of the listed to...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. We are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world's most advanced technol...

At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation and SoC Design, we want to meet you. Job Description And Requirements The role is for SoC Verification in the System Solutions Group (SSG). The role primarily requires development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service projec...

Verification Test bench development and debug UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based testing. Coverage analysis (code, functional, assertion) Verification plan reviews, Verification reviews Back-annotated netlist simulation execution and debug Debug failing cases & Coverage improvements.

Key roles and responsibilities: - Underwrite complex Property and Engineering risks in accordance with company guidelines and market standards. Conduct technical risk assessments, pricing, and coverage analysis to support underwriting decisions. Actively engage in techno-marketing initiatives, presenting technical solutions and value propositions to clients and intermediaries. Liaise effectively with brokers, agents, and internal sales teams to promote insurance products and close profitable business. Support business development efforts through market intelligence and client relationship management. Ensure all underwriting activities comply with internal controls, underwriting guidelines, a...

As a member of the team working on custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation behind products that are beloved by millions worldwide, delivering exceptional performance, efficiency, and integration. **Key Responsibilities:** - Collaborate with architects to develop microarchitecture - Perform Verilog/SystemVerilog RTL coding - Conduct functional/performance simulation debugging - Carry out Lint/CDC/FV/UPF checks - Participate in test planning and coverage analysis - Develop RTL implementations meeting power, performance, and area goals - Be involved in ...

Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff include formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product arch...

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff include formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for cu...

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing a...

You will be responsible for developing and executing AMS verification plans for mixed-signal IP and SoCs. This includes creating and validating behavioral models using Verilog-A for analog and mixed-signal blocks. You will also implement and optimize AMS testbenches in the Xcelium simulation environment. Collaboration with analog and digital designers is a key aspect of this role, as you will work together to verify top-level integration and system performance. Additionally, you will be expected to debug and resolve complex AMS simulation and modeling issues. In order to drive continuous improvement, you will contribute to the development of AMS verification methodologies and best practices....

You are a driven and meticulous ASIC Digital Verification Engineer, keen to make a significant impact in the semiconductor industry. You possess a strong foundation in digital verification methodologies and have a keen eye for detail. With a collaborative spirit, you thrive in a team environment while also excelling when working independently. Your communication skills are top-notch, allowing you to articulate complex technical concepts with ease. You are passionate about innovation and are always looking for ways to improve processes and outcomes. Your proficiency in UVM and SystemVerilog, combined with your programming skills in languages such as C, TCL, Perl, or Python, positions you as a...

As a Design Verification Engineer with over 5 years of experience, particularly in HBM & DDR DRAM IP and Subsystem verification, you will be an integral part of our innovative team. Your role will involve developing and executing verification plans, creating testbenches, and collaborating with design engineers to ensure high-quality and robust designs. Your responsibilities will include developing comprehensive verification plans for HBM4/4e IP and Subsystem, creating and maintaining testbenches using System Verilog and UVM methodology, performing functional verification of RTL designs, and resolving design and verification issues. You will also generate verification metrics, participate in ...

As a Senior DFT engineer with over 10 years of experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, and LBIST, you will play a crucial role in ensuring the design quality and functionality of complex semiconductor devices. Your educational background should include a BE/ME/B.Tech/M.Tech degree from reputed institutes with a 1st class degree and a minimum of 5 years of relevant industry experience. Your expertise in Verilog/VHDL RTL coding and proficiency in using Mentor DfT tools and Cadence tools will be essential for success in this role. You will be responsible for tasks such as scan insertion, JTAG, LBIST, ATPG, DRC, and coverage analysis,...

You Are: You are a highly skilled and experienced SoC Verification Lead with a passion for pushing the boundaries of technology. With a minimum of 5 to 20Years of experience in the SoC/IP/Subsystems verification domain, you possess deep technical expertise in various aspects of pre-silicon verification, including UVM, coverage analysis, verification plan creation, and debugging. You have a strong understanding of design concepts and ASIC flows, and you are adept at leading teams to perform verification on complex SoC/IP/Subsystems. Your knowledge of protocols such as PCIe, Ethernet, USB, and DDR, along with your hands-on experience with verification tools like VCS, waveform analyzers, and th...

As an Electrical Engineer or Computer Science professional with a Bachelor's degree and 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon, you will have the opportunity to contribute to the innovation behind Google's direct-to-consumer products. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Your responsibilities will include defining the microarchitecture of IPs, Subsystems, or SOCs, working with cross-functional teams to ensure quality, schedule compliance, and PPA optimized design. You will collaborate with Verification, Design for Test, Physica...

Hiring for Motor insurance and Body injury claims specialist Location: whitefield Education : graduation Salary : upto 6LPA minimum 1.5 years into the specified domain Sat,Sun fixed off ,2 way cab Fixed UK shift Immediate joiners or with in 15 days

Hiring for Medical Underwriters- Health Insurance Only M.B.B.S - BPT, BDS, BMS, MPT Job Role- To assess the risk associated with insuring individuals or groups, evaluate medical history, and determine policy terms, coverage limits, and premiums, all while adhering to company policies and industry regulations. Experience Required - Minimum 2+Years of Experience Locations - Gurgaon Chennai (Tamil) Kochi (Malayalam) Interested candidates can directly share their resumes on simranbagga@policybazaar.com or 9311501270

The position of AMS Verification Lead Led Model is currently open in Bangalore with 1+5 positions available. We are looking for individuals with 2 to 12+ years of experience in this field. Key Responsibilities: - Developing and executing AMS verification plans for mixed-signal IP and SoCs. - Creating and validating behavioral models using Verilog-A for analog and mixed-signal blocks. - Implementing and optimizing AMS testbenches in the Xcelium simulation environment. - Collaborating with analog and digital designers to verify top-level integration and system performance. - Debugging and resolving complex AMS simulation and modeling issues. - Driving and contributing to the development of AMS...