You will be responsible for design verification at chip level to ensure that the design meets architectural and system requirements. This includes developing test environment, test bench, bus protocol checking, transaction level checking, and performance modeling. Experience in advanced verification languages such as VERA, Specman, and System C is desirable. You should have 3-5 years of solid design verification experience. A minimum educational requirement is a BS in EE, while an MS in EE is preferred. If you are interested in this position, please email your resume to careers@perfectus.com with Job Code VE in the subject line.,

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ASIC Design Verification