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ACL Digital
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Asic Design And Verification Engineer

Asic Design And Verification Engineer

ACL Digital

3 - 8 years

17 - 25 Lacs

Pune Bengaluru

Posted:2 months ago| Platform:

Apply

Skills Required

SV C SOC CPU UVM C++ Ip Verification

Work Mode

Work from Office

Job Type

Full Time

Job Description

Job Title:

Location:

Industry:

Job Overview:

Verification Engineers

Key Responsibilities:

Develop
testbenches
using
SystemVerilog (SV)
and
UVM methodology
Create, execute, and maintain
test cases
for functional and directed/random verification
Work on
IP-level, SoC-level
, or
CPU verification
based on project allocation
Perform
debugging, coverage analysis
, and
assertion-based verification
Collaborate with RTL designers, architects, and verification leads to ensure comprehensive test coverage
Review and contribute to verification plans and specifications

Must-Have Skills:

3.5 to 6 years
of experience in ASIC/SoC/IP verification
Strong hands-on expertise in
SystemVerilog and UVM
Proficient in
testbench architecture and test case development
Good debugging and problem-solving skills
Experience with simulation tools like
VCS, Questa, Incisive
, etc.
Exposure to code coverage, functional coverage, and regression analysis

Good to Have:

Prior experience in
CPU or SoC level
verification
Familiarity with scripting (Python, Perl, Shell)
Knowledge of formal verification and assertion-based techniques

Why Join Us?

Work on
next-gen ASIC and SoC technologies
Opportunity to collaborate with
top semiconductor minds
Dynamic, inclusive work environment with strong technical mentorship
Accelerated career growth with challenging project exposure

If you're available to join within 15 days and meet the above criteria, we want to hear from you!

Apply now with your updated resume and notice period.

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