MLB / SMT Failure Analysis - EMS Industry Tata Electronics

10.0 - 18.0 years

0 Lacs

hosur, tamil nadu

On-site

You are invited to join our team as an SMT/ MLB Failure Analysis Engineer at the position of Asst Manager / Deputy Manager with 10-18 years of experience. The job is based in Hosur. As an SMT / MLB Failure Analysis Engineer, you will be responsible for leading complex failure analysis of MLBs and SMT assemblies using advanced diagnostic tools such as X-ray, SEM, ICT, and AOI. Your role will involve performing root cause analysis on field returns, in-process failures, and customer complaints. You will develop and implement corrective and preventive actions to eliminate recurring issues while collaborating with design, process, and quality teams to enhance product and process robustness. Analyzing yield trends and driving continuous improvement initiatives will be a key part of your responsibilities. Additionally, you will be required to prepare detailed technical reports, present findings to internal and external stakeholders, mentor junior engineers and technicians in failure analysis methodologies and tools, and ensure documentation compliance with industry standards such as IPC, ISO, and IATF. To excel in this role, you should possess a Bachelors or Masters degree in Electronics, Electrical Engineering, or a related field along with 10-15 years of hands-on experience in failure analysis within the EMS industry. Your strong knowledge of SMT processes, PCB design, and component-level diagnostics will be essential. Proficiency in tools like oscilloscopes, multimeters, X-ray, SEM, FIB, and thermal imaging is required. Familiarity with IPC standards (IPC-A-610, IPC-7711/7721) and quality systems such as ISO 9001 and IATF 16949 will be advantageous. Excellent analytical, documentation, and communication skills are also crucial for success in this role. If you are seeking a challenging opportunity to apply your expertise in failure analysis and contribute to continuous improvement efforts in a dynamic environment, we encourage you to apply for this position. We look forward to welcoming you to our team. Best Regards, Team HR,

Posted 2 days ago

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Design for Testability Engineer Google

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a candidate for the role, you should possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or have equivalent practical experience. Additionally, you need to have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, including managing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial that you have familiarity with ATPG, Low Value (LV), Built-in Self Test (BIST), or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications for this position include proficiency in a programming language such as Perl, along with experience in Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC), DFT timing, and Static Timing Analysis (STA). An understanding of performance design DFT techniques, end-to-end flows in Design, Verification, DFT, and Partner Domains (PD), as well as the ability to scale DFT will be advantageous. Joining our team means being part of a group that continually pushes boundaries, focusing on developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in the innovation that underpins products adored by millions globally. Your expertise will be instrumental in shaping the next wave of hardware experiences, delivering unmatched performance, efficiency, and integration. At Google, our mission is to organize the world's information and make it universally accessible and useful. Our collaborative team leverages the best of Google AI, Software, and Hardware to create exceptionally helpful experiences. We are dedicated to researching, designing, and developing new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to enhance people's lives through technology. In this role, your responsibilities will include collaborating with a team focusing on Design for testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, and Static Timing Analysis (STA) checks. You will be tasked with writing a Pattern delivery using Automatic Test Pattern Generation (ATPG), contributing to Silicon bring-up, working on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug, and delivering debug patterns, as well as performing Silicon data analysis.,

Posted 5 days ago

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