928 Vhdl Jobs - Page 28

Category Engineering Hire Type Employee Job ID 9331 Remote Eligible No Date Posted 06/02/2025 Applications Engineer position offers a wonderful opportunity to work on most challenging technical problems in verification domain and innovative technologies under Synopsys Verification Platform. Looking for an experienced and motivated professional who enjoys problem solving, open to continuous learning, passionate to work on cutting edge technologies and has excellent communication skills. It gives exposure to the breadth of HDL/HVL, methodologies, static and formal verification, dynamic simulation aspects including debug and experience in working in a diverse environment where interaction with domain experts across global locations will be involved. Key Requirements Experience: Bachelor’s degree in Electronics with 7+ Years’ or Master’s degree in Electronics with 5+ Years' Experience in verification technologies (Simulation, UVM, SVA, LRM understanding) Strong HDL language support (Verilog, VHDL, System Verilog) Simulation, UVM, Design Verification Digital design fundamental and RTL coding understanding Good Debugging skills. Scripting – Perl, TCL, Make, Shell Scripting. Role - VCS Simulation Technology Product Engineer Solid fundamentals in Digital design, HDLs (Verilog/VHDL) and System Verilog Exposure to Synopsys EDA tools (SpyGlass, VC SpyGlass, Verdi) would be added advantage Excellent written and oral communication skills is a must as the role requires interfacing global teams, proposing solutions Must have working knowledge on UNIX, TCL and/or any other scripting language to be effective Team player, partners with multiple stakeholders, has attention to detail and innovative mindset Motivated, doer and self-organized team worker with good social communication skills Open to travel, ability to multi-task, be detail-oriented Drive VCS/related technology customer deployment working closely with field and R&D Drive competitive engagements, requirements gathering for delivery strong product roadmap Work directly with R&D, Product Validation & Customers to suggest improvements in implementation and validation Use in-depth product understanding to provide technical expertise, diagnose, troubleshoot issues At Synopsys, we’re at the heart of the innovations that positively impact the world. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you echo our passion for innovation, we want to meet you. Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10482 Remote Eligible No Date Posted 13/04/2025 Sr, Staff ASIC Verification Engineer, Noida Location: Key responsibilities: Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …) Generate verification test plan, verification environment documentation and test environment usage documentation Define, develop, and verify complex UVM verification environments Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers , VIP team to accomplish tasks. Identify design problems, possible corrective actions and/or inconsistencies on documented functionality Work with peers to improve methodologies and improve execution efficiency. Adhere to quality standards and good test and verification practices. Work as a lead, mentor junior engineers, and help them in debugging complex problems. Able to Support Customer issues, by their reproduction and analysis. Should be able multitask between different activities. Key Qualifications Proven desire to learn and explore new state of the art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM . Good organization and communication skills Be a solution provider. 8+ years of relevant experience At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10019 Date posted 03/17/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled R&D Staff Engineer passionate about pushing the boundaries of static low power verification products. With 5 to 8 years of experience in software engineering, you have honed your expertise in C/C++ and possess a robust understanding of data structures and algorithms. Your background in Electronic Design Automation (EDA) tools and methodologies, coupled with your knowledge of Verilog, SystemVerilog, and VHDL, positions you as a leader in your field. You are a proactive problem-solver with a keen eye for detail, and you thrive in collaborative environments where you can lead and inspire a team. Your self-motivation and discipline drive you to set and achieve personal goals consistently, and your commitment to quality ensures that your contributions make a significant impact. Based in Noida or Bangalore, you are ready to take on new challenges and help shape the future of technology. What You’ll Be Doing: Designing and developing state-of-the-art EDA tools with innovative algorithms. Collaborating with local and remote teams to ensure seamless integration and execution. Working directly with customers to understand requirements, provide online debugging, and track delivery and execution. Leading a small team of 2-3 members, guiding them through technical challenges and project milestones. Contributing to the continuous improvement of our static low power verification product. Exploring new architectures and leading the charge in developing cutting-edge solutions. The Impact You Will Have: Driving the development of advanced EDA tools, contributing to the efficiency and effectiveness of chip design. Enhancing the quality and reliability of our static low power verification product. Providing critical support to customers, ensuring their needs are met and fostering long-term relationships. Leading and mentoring junior engineers, fostering a culture of innovation and excellence within the team. Contributing to Synopsys' reputation as a leader in the semiconductor and EDA industries. Playing a pivotal role in the successful execution of projects, meeting deadlines, and exceeding expectations. What You’ll Need: Fluency in C/C++ with a strong background in data structures and algorithms. Experience with UPF and familiarity with Tcl and Python-based development on Unix (preferred). Knowledge of Verilog, SystemVerilog, and VHDL HDL (preferred). Experience with production code development on Unix/Linux platforms. Ability to develop new architectures and demonstrate strong leadership skills. Who You Are: You are a dynamic and innovative engineer with a passion for technology and a commitment to quality. You possess excellent problem-solving skills and the ability to think critically and creatively. As a self-motivated individual, you set personal goals and work diligently to achieve them. Your leadership skills enable you to guide and inspire your team, fostering a collaborative and productive work environment. You are detail-oriented, ensuring that your work meets the highest standards of quality and reliability. Your experience in EDA tools and methodologies, coupled with your knowledge of hardware description languages, positions you as a valuable asset to our team. The Team You’ll Be A Part Of: You will be part of the Static Verification team, a group of talented engineers dedicated to developing and enhancing our static low power verification products. This team collaborates closely with other departments, including design, development, and customer support, to ensure seamless integration and execution. Together, you will work on cutting-edge projects that push the boundaries of technology and contribute to the success of Synopsys and its customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Description / Summary Join our elite North America hardware application engineering team, and work closely with the best AEs, PEs and R&D in EDA industry. Join a top class company that has been listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ for the eleven years in a row! You will report directly into the North America Verification Field Applications Engineering (FAE) Team, and be co-located in India alongside our R&D teams. You will be a leading product expert on advanced FPGA based prototyping focusing on Cadence’s Protium X3 system . Your focus will be to work on key campaigns in North America, driving differentiated HW emulation solutions at our industry leading semiconductor and system companies and you will form a key bridge between our customers, North America AEs and R&D teams. Key Responsibilities Assume technical leadership for Protium compiler flow and become the go-to expert for the rest of the North America field AE team . Provide in-depth technical assistance in collaboration with R&D to help support advanced Protium based flows to secure design wins . Champion the customer needs and work closely with R&D in India to develop competitive and creative technical solutions. Strong experience in FPGA based emulation or prototyping. Experience in portioning for Xilinx FPGA’s and analyze bottlenecks to performance. Knowledge of interface bring up on FPGA platforms like PCIe and DDR Experience with SystemVerilog, VHDL, Verilog, C/C++/SystemC Strong verbal and written communication skills, with the ability to effectively bridge communication channels between external customers, NA FAE team and internal R&D teams. Strong teamwork skills 12+ years industry experience We’re doing work that matters. Help us solve what others can’t.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10738 Date posted 04/23/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 5 -8 years of experience, you bring a wealth of knowledge in software architecture and leadership. You excel in C/C++ software development, and your strong background in design patterns, data structures, and algorithms sets you apart. You thrive in multi-threaded and distributed code environments, and your familiarity with ASIC design flow and EDA tools is second to none. Your expertise in Verilog, SystemVerilog, and VHDL HDL, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind, and you understand the importance of source code control tools such as Perforce. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: - Designing, developing, and troubleshooting core algorithms for word-level synthesis. - Collaborating with local and global teams to enhance synthesis QoR, performance, and logic interference. - Engaging in pure technical roles focused on software development and architecture. - Implementing multi-threaded and distributed code solutions. - Utilizing your knowledge of ASIC design flow and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL HDL to develop cutting-edge solutions. The Impact You Will Have: - Driving technological innovation in chip design and verification. - Enhancing the performance and quality of synthesis tools used globally. - Solving complex logic interference problems to improve design accuracy. - Contributing to the development of high-performance silicon chips and software content. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: - Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Familiarity with multi-threaded and distributed code development. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: - Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the word-level synthesis team, catering to multiple EDA products. This team focuses on developing innovative solutions to improve synthesis quality of results (QoR), performance, and logic interference. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10481 Remote Eligible No Date Posted 13/04/2025 Staff ASIC Verification Engineer, Noida Location: Key responsibilities: Participate in development of verification test plan, verification environment documentation and test environment usage documentation Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers , VIP team and peers to accomplish all verification goals. Identify design problems, possible corrective actions and/or inconsistencies on documented functionality Adhere to quality standards and good test and verification practices. May work to coach junior engineers and help them in debugging complex problems. Key Qualifications Proven desire to learn and explore new state of the art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM . Good organization and communication skills. 5 + years of relevant experience At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 9672 Date posted 03/02/2025 Candidate will be part of VC PS Noida team. Design, develop, troubleshoot the core algorithms. Design and develop standard and customized features / checks in VC PS for inference, propagation and verification. Will be working with other local and global teams. Design and development of state of the art EDA tools involving development of new and innovative algorithms. Create test cases to test the developed feature. Skills Required Ability to develop new software architecture and good leadership skills. Fluent in C/C++ with extensive work experience in data-structures and algorithms. Excellent algorithm analysis skills and a good knowledge of data structures. Good knowledge of Tcl and Perl-based development on Unix. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Familiarity with multi-threaded and distributed code development. Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Quality focus - one who believes in quality and wants to make a difference. Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Looking for Siemens EDA ambassadors We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us – whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the R&D team, you will contribute to Siemens’ success by crafting state of the art power analysis and optimization solutions. This is your role Analyzer team is working on the development of front end (Analyzer and Elaborator) of different Mentor Compilers. This module takes care of various HDL languages like Verilog, System Verilog and VHDL. As a member of the team, one will be working primarily on C++ and flex/bison and will be responsible for the design, development modify, and implementation of various pieces of the overall software with focus on surpassing customer expectations, on achieving high quality and timely delivery. Responsible for ensuring the overall functional quality of the released product on all required platforms and mechanism. Ability to understand complex products, solutions, and problems. Builds, documents, and executes software designs which may involve complicated workflows or multiple product areas. We are not looking for superheroes, just super minds We are seeking a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/Computer Science (CS) from top reputed Engineering colleges with significant experience in software development with 1-4 Years of experience. We value sound understanding of C/C++ languages, design patterns along with data structure and algorithms will be key to development of software. Experience in parallel algorithms, job distribution. Experience in development of Front End EDA software is a plus! Proficiency in HDL languages – Verilog/VHDL/System Verilog - low power aware synthesis and power formats - UPF/CPF – will supplemental. We are looking for knowledge of flex/bison and understanding of gate level digital logic design. Good analytical, abstraction and interpersonal skills will help in crafting bigger and balanced solutions for complex systems. Ability to work individually and as a team player will help in crafting good solutions and should be able to guide other towards project completion. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. #LI-EDA #LI-HYBRID

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Role Description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures Of Outcomes Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely Delivery Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills Development Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments Job description: PHY design Experienced analog/mixed-signal designer for high-speed PHYs design. It is mandatory that the candidate has in-depth understanding of analog and mixed-signal design, with hand-on design experience of PHY circuits. Specific areas of expertise/knowledge required: Voltage & current references, LDO regulator, high-accuracy comparator and amplifier High speed custom digital circuits like serializer, de-serializer, clock divider and synchronizer High Speed flops, gates operating at low voltage with best in class PPA Voltage and current mode transmitters, duty-cycle corrector TX/RX equalization techniques and circuits (e.g. CTLE, DFE) Calibration technique to tune for PVT variation Mixed mode simulation Transmission line theory, concept of PDN, device mismatch, system linearity and stability, low power design Following areas would be a significant Plus: Skills in scripting and automation Knowledge of common PHY protocols (DP, USB, Ethernet etc.) Concept of Quality in design and IP delivery Understanding of behavioral modeling of Analog circuits and RTL-to-GDS flow Skills Analog Mixed Signal ,PHY Circuit ,LDO regulator Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Role Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Skill Set Proficiency in Python/Tcl Familiar with Synthesis tools (Fusion Compiler/Genus), Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus Should be sincere, dedicated and willing to take up new challenges Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075441 Show more Show less

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

Experience : 4+ years Location: Chennai, Bangalore, Noida, Hyderabad, Cochin Responsibilities: Develop RTL code for complex digital circuits using Hardware Description Languages (HDLs) such as Verilog or VHDL Perform functional verification using simulation and formal methods Participate in code reviews and ensure adherence to coding standards Analyze timing performance and perform static timing analysis (STA) Collaborate with design, verification, and synthesis teams to ensure successful tape-out Stay up-to-date with the latest RTL design methodologies and tools Show more Show less

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 11861 Date posted 06/03/2025 Description Candidate will be part of TCM Front End team. Design, develop, troubleshoot the core algorithms used in TCM Front End tool Design and develop standard and customized features / checks in TCM FE for seamless consumption of VCS OM. Will be working with other local and global teams of TCM and VC SpyGlass Design and development of state-of-the-art EDA tools involving development of new and innovative algorithms. Create test cases to test the developed feature. Skills Required Strong knowledge of Front-end compilers and their flow Ability to develop new software architecture and good leadership skills. Fluent in C/C++ with extensive work experience in data-structures and algorithms. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Excellent algorithm analysis skills and a good knowledge of data structures. Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Familiarity with multi-threaded and distributed code development. Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Quality focus - one who believes in quality and wants to make a difference. Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated engineer to be part of the Modus R&D team, with a focus on validating and supporting Design-for-test (DFT) technologies. Candidate must have 2+ years of experience in DFT/ATPG/ASIC Design flows and knowledge of RTL Verilog/VHDL coding styles, Synthesis. This position requires excellent communication skills (written and oral) to interface with Product Engineers (PEs) and R&D and will occasionally also involve direct customer support responsibilities. Will work on complex problems that require innovative thinking, debugging customer reported problems and collaboration with R&D to propose out-of-box solutions with emphasis on robustness, PPA and scalability. Role Responsibility Work as a DFT Product Validation Engineer on insertion and validation of DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST etc. using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer designs. Create testplans for verification of new features and execute them by creating new test cases requiring application of Design & DFT skills; Report bugs/enhancements in tool. Collaborate with R&D and Product Engineering teams to review feature specifications, testplans & customer issues. Debug issues reported by customers and suggest/implement measures to plug the gaps. Position Requirements B.E/B.Tech with 2+ years or M.E/MTech in Electronics/Electrical of experience Strong in Digital electronics, Verilog Good understanding of DFT techniques and methodologies Familiarity with Test standards like 1149.1, 1500, 1687 is a plus Experience with Cadence Test or other Test tools is preferred Modus is a DFT (Design for Testability) software tool from Cadence used by leading chip design companies during DFT synthesis & ATPG (Automatic Test Pattern Generation) phase of chip design We’re doing work that matters. Help us solve what others can’t. Show more Show less

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Looking for Siemens EDA ambassadors We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us – whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the R&D team, you will contribute to Siemens’ success by crafting state of the art power analysis and optimization solutions. This is your role Analyzer team is working on the development of front end (Analyzer and Elaborator) of different Mentor Compilers. This module takes care of various HDL languages like Verilog, System Verilog and VHDL. As a member of the team, one will be working primarily on C++ and flex/bison and will be responsible for the design, development modify, and implementation of various pieces of the overall software with focus on surpassing customer expectations, on achieving high quality and timely delivery. Responsible for ensuring the overall functional quality of the released product on all required platforms and mechanism. Ability to understand complex products, solutions, and problems. Builds, documents, and executes software designs which may involve complicated workflows or multiple product areas. We are not looking for superheroes, just super minds We are seeking a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/Computer Science (CS) from top reputed Engineering colleges with significant experience in software development with 1-4 Years of experience. We value sound understanding of C/C++ languages, design patterns along with data structure and algorithms will be key to development of software. Experience in parallel algorithms, job distribution. Experience in development of Front End EDA software is a plus! Proficiency in HDL languages – Verilog/VHDL/System Verilog - low power aware synthesis and power formats - UPF/CPF – will supplemental. We are looking for knowledge of flex/bison and understanding of gate level digital logic design. Good analytical, abstraction and interpersonal skills will help in crafting bigger and balanced solutions for complex systems. Ability to work individually and as a team player will help in crafting good solutions and should be able to guide other towards project completion. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position: Principal Software Engineer Location: Noida Job Responsibilities: The role s day to day responsibilities cover: R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications: BE/BTech/ME/MTech- Computer Science or others Experience: 10-15 Years Required Skills The successful candidate will possess the following combination of education and experience: Proficient in C/C++ Excellent programming and software engineering skills Experience with UNIX and/or LINUX platforms is preferred RTL knowledge - System Verilog, VHDL is preferred Strong knowledge of Tcl is preferred Experience in language compiler Prior experience with large software development projects is highly recommended Prior experience with timing analysis software development projects is highly recommended Data structure and algorithmic skills We re doing work that matters. Help us solve what others can t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: We are looking for 14+ years of experience having the following skillset: Strong RTL design fundamentals using HDLs like VHDL/Verilog/System verilog Strong understanding of AMD (Xilinx) ultrascale, versal FPGAs architecture and use of vivado for FPGA place and route. Constraints definitions for FPGAs. Doing Static Timing Analysis. Familiarity with FPGA prototyping or emulation is a plus. Passionate to learn and explore new technologies and demonstrates good analysis and problem-solving skills. Good written and verbal communication skills, should be a quick learner and a team player. We re doing work that matters. Help us solve what others can t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Description / Summary Join our elite North America hardware application engineering team, and work closely with the best AEs, PEs and R&D in EDA industry. Join a top class company that has been listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ for the eleven years in a row! You will report directly into the North America Verification Field Applications Engineering (FAE) Team, and be co-located in India alongside our R&D teams. You will be a leading product expert on advanced virtual interface solutions such as Accelerated Verification IP’s and Virtual Bridges solutions for Cadence’s hardware emulation and prototyping platforms. Your focus will be to work on key campaigns in North America, driving differentiated HW emulation solutions at our industry leading semiconductor and system companies and you will form a key bridge between our customers, North America AEs and R&D teams. Key Responsibilities Assume technical leadership for all virtual interface solutions for Palladium and Protium and become the go-to expert for the rest of the North America field AE team . Provide in-depth technical assistance in collaboration with R&D to help support advanced emulation flows to secure design wins . Champion the customer needs and work closely with R&D in India to develop competitive and creative technical solutions. Requirements Strong experience in hardware emulation with knowledge of interface protocols like PCIe , AMBA and Ethernet Experience in synthesizable coding style Knowledge of fundamental SoC Architectures Experience with SystemVerilog, VHDL, Verilog, C/C++/SystemC Ability to quickly analyze emulation environments and design complexity. Strong verbal and written communication skills, with the ability to effectively bridge communication channels between external customers, NA FAE team and internal R&D teams. Strong teamwork skills 8+ years industry experience We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Description / Summary Join our elite North America hardware application engineering team, and work closely with the best AEs, PEs and R&D in EDA industry. Join a top class company that has been listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ for the eleven years in a row! You will report directly into the North America Verification Field Applications Engineering (FAE) Team, and be co-located in India alongside our R&D teams. You will be a leading product expert on advanced virtual interface solutions such as Accelerated Verification IP’s and Virtual Bridges solutions for Cadence’s hardware emulation and prototyping platforms. Your focus will be to work on key campaigns in North America, driving differentiated HW emulation solutions at our industry leading semiconductor and system companies and you will form a key bridge between our customers, North America AEs and R&D teams. Key Responsibilities Assume technical leadership for all virtual interface solutions for Palladium and Protium and become the go-to expert for the rest of the North America field AE team . Provide in-depth technical assistance in collaboration with R&D to help support advanced emulation flows to secure design wins . Champion the customer needs and work closely with R&D in India to develop competitive and creative technical solutions. Requirements Strong experience in hardware emulation with knowledge of interface protocols like PCIe , AMBA and Ethernet Experience in synthesizable coding style Knowledge of fundamental SoC Architectures Experience with SystemVerilog, VHDL, Verilog, C/C++/SystemC Ability to quickly analyze emulation environments and design complexity. Strong verbal and written communication skills, with the ability to effectively bridge communication channels between external customers, NA FAE team and internal R&D teams. Strong teamwork skills 8+ years industry experience We’re doing work that matters. Help us solve what others can’t.

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role In this role, you will focus on the verification of CPU and chip-die (Cdie) level Power Management features for our server-class microprocessors. Your work will ensure that our processors achieve optimal power efficiency without compromising performance. You will collaborate closely with architecture, design, and post-silicon teams to validate and debug power management features, contributing to our cutting-edge AI compute solutions. As part of our team, you will be at the forefront of innovation, helping us deliver high-performance, energy-efficient products. The Design Verification team at Ampere is dedicated to ensuring that every product meets the highest standards of quality and efficiency. We are a collaborative, fast-paced group, committed to leaving no stone unturned in our verification processes. What You’ll Achieve Define requirements for power management verification at both sub-system and full-chip levels. Develop detailed test plans focused on power management features for both pre-silicon and post-silicon environments. Architect, design, and implement test benches and verification environments specifically for power management. Create targeted and random test generators to identify power-related bugs. Analyze and debug power management failures, driving rapid resolution. Develop coverage monitors and achieve targeted coverage metrics for power management features. Define and execute post-silicon validation plans for power management, supporting accelerated product launches. About You B.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience, or M.Tech with 2+ years of experience. Strong experience in hardware verification, particularly in power management for IPs or SoCs. Proficient in industry-standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools. Experience in developing verification environments using languages such as SVTB UVM/OVM. Proficiency in programming languages like C, C++, Perl, and Python for automation tasks. Experience in automating design, verification, and validation tasks related to power management. Familiarity with ARM, RISCV, or x86 assembly language programming is beneficial. Understanding of CPU architecture, power management techniques, coherent fabrics, and interconnects is a plus. Excellent written and verbal communication skills, with a strong attention to detail and analytical/problem-solving abilities. What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law. Show more Show less

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.  Listener, Understander, Doer. Customers around the world trust in our products and our application engineers significantly contribute to that. You are the first on the scene to tackle any technical problem. You are a competent adviser, team player, and make things possible. “Unsolvable” is a foreign term, and you don’t do “unfair.” Your focus on the customers’ needs makes you an invaluable partner. When you join our team, you will reach one hundred percent in your career. As an integral part of the technical team, you will contribute to Siemens EDA by increasing productivity and customer satisfaction Siemens EDA’s Verification platform. This is an ambitious position that will assist in growing Siemens's business in India. Your new role: results-oriented and futuristic · You will be working collaboratively with customers as well as customer support and engineering teams to optimally deploy Siemens EDA’s Questa products and services. · You’ll fosters a climate conducive to help grow customer satisfaction with Siemens’ tools by helping them successfully deploy new flows and methodologies. · Optionally mentor and lead a team of application engineers, supervise and guide them on the accounts and engagements that they are working on. · You’ll be working with customers with varying design styles and methodologies to craft the most effective technical solutions. · You’ll provide key expert advice and contribute to technical campaigns in other regions. · Identify and qualify potential new business opportunities and work the account teams to build an engagement plan. · Work with Account Managers and the world-wide teams for forming strategies and driving Siemens’ tools for customer projects to enable business success for Siemens EDA. · Become a trusted advisor to your customers. · Will have moderate travel within India and abroad We are not looking for superheroes, just super minds · You’re a Graduate / Post Graduate (Bachelors/Masters) Electronics and Communication (E&C) / Electrical / Telecom Engineering / Computer Engineering with 4 - 10 years of meaningful experience in Digital design and Clock Domain Crossing or Lint EDA tools. · You’ve solid understanding on VHDL/Verilog, SystemVerilog and Assertions. · Well versed with Multiple Clock and Reset Domains and Asynchronous clock or reset domain crossing verification ( Clock Domain Crossing - CDC & Reset Domain Crossing - RDC ) on designs · Expertise in CDC tools like Questa/0in CDC, Spyglass or VC- CDC, or other CDC products is expected · Expertise in Formal Verification products like Questa Formal, Jasper or any other Formal products is a plus · Low power verification techniques using UPF and CPF is a plus · Exposure to static timing analysis (STA) flows involving SDC is a plus We’ve got quite a lot to offer. How about you? This role is based in Noida and you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. Siemens EDA is a world leader in EDA Tools business and has been present in India since 1997. We, at Siemens EDA, enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design. Show more Show less

🚀 About the Role We're hiring an experienced FPGA Firmware Engineer to develop and integrate high-speed digital systems for cutting-edge defence and aerospace applications. You'll work on complex RTL logic, high-speed interface protocols like 10G Ethernet and JESD204B/C, and mentor junior engineers in a mission-critical development environment. If you’re passionate about FPGA design and want to contribute to indigenous strategic technologies, we’d love to meet you. 📍 Location : Chennai | 🕒 Full-Time | 🧭 Experience : 3–5 Years No. of Vacancy : 01 🎯 What You’ll Do Design and implement RTL code (VHDL/Verilog) for FPGA-based systems (Xilinx/Intel). Integrate and validate 10G Ethernet, JESD204, and AXI-based IP cores. Collaborate with hardware teams for board bring-up and system-level debugging Optimise firmware for high-speed data processing, signal acquisition, and control loops. Simulate, verify, and debug designs using tools like Vivado, ModelSim, and Logic Analysers. Mentor a team of junior engineers and ensure adherence to coding standards. Contribute to documentation and compliance (DO-254, AS9100). Interface with cross-functional teams, including QA, hardware, and system engineering. ✅ What We’re Looking For B.E./ B.Tech or M.E./ M.Tech in ECE, EE, or related fields. 3–8 years of FPGA development experience in defence/aerospace or high-reliability domains. Hands-on experience with Vivado/Quartus, ModelSim/QuestaSim, and constraint-based timing closure. Strong understanding of 10G Ethernet, JESD204B/C, CDC, and high-speed digital design. Proficiency in scripting (Tcl, Python) and hardware debugging tools. Experience working with embedded soft cores (MicroBlaze, Zynq, or Nios II) is a plus. Team leadership or mentoring experience preferred. 🌐 Nice to Have Worked on radar, EW, or signal processing systems. Familiarity with MIL-STD, ARINC 818, or custom defence protocols. Prior engagement with DRDO, BEL, HAL, or Indian defence projects. 🛡 Why Join Us Work on indigenous, mission-critical defence systems. Be part of a growing high-tech R&D environment. Get opportunities to lead, innovate, and mentor. Secure and process-driven workplace with a focus on national development. Tips: Provide a summary of the role, what success in the position looks like, and how this role fits into the organisation overall. 📩 Apply Now If you're ready to take the lead on high-performance FPGA systems and mentor the next generation of engineers, apply now or send your profile to admin@indrainsignia.co.in Show more Show less

Job Title: Senior Engineer - FPGA Location: Ahmedabad, Pune, Bangalore Experience level: 5+ Years In depth knowledge with VHDL/Verilog/System Verilog, RTL design, FPGA design, and FPGA design tools. Complete FPGA development flow from logic design, place & route, timing analysis closure, simulation, verification, and validation Experience with Xilinx/Intel FPGA families and corresponding development tools Vivado/Quartus Experience in verification/simulation tools Modelsim/Questa-sim etc. Troubleshooting and debugging FPGA implementations on hardware boards Experience with debugging HW/SW issues and the use of equipment/tools such as oscilloscope, logic analyzer, Chipscope/ILA/Signal Tap Ability to understand synthesis reports, perform timing analysis and write FPGA design constraints Hands-on experience on communication protocols (UART/I2C/SPI etc.) and bus interfaces (AMBA/AXI etc.) Good understanding of digital electronics and design practices Ability to work independently as well as in team Effective interpersonal, communication, presentation and reporting skill Qualifications: Minimum B.E./B.Tech in Electronics/E&TC/ECE About eInfochips · eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company’s service offerings include digital transformation and connected IoT solutions across various cloud platforms, including AWS and Azure. Along with Arrow’s $30B in revenues, 20,100 employees, and 349 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 200,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients through Arrow Connect. InfochipsInc. is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, sexual orientation, genderidentity, national origin, veteran or disability status. eInfochips (Arrow) COVID-19 Vaccination Policy: eInfochips (Arrow) requires employees to provide proof of full COVID-19 vaccination by December 1, 2021, for all positions located in CO and for business units within immix Group and Zeus. All other employees will be required to identify vaccination status by December 1, 2021. Arrow COVID-19 Vaccination Policy: Arrow requires all new employees in the United States to provide proof of full COVID-19 vaccination prior to beginning work, except where prohibited by law. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL Design and implement RTL for DFT IP incl. POST, IST Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verification Own and maintain, extend, and enhance existing DFT IP like LBIST We’re doing work that matters. Help us solve what others can’t. Show more Show less