Posted:1 week ago|
Platform:
On-site
Full Time
Experience : 8+ years
Location : Bangalore
Role Overview:
Owns property-based formal verification of the CPU core, pipeline stages, and subcomponents with exhaustive proof goals.
Key Responsibilities:
• Lead formal planning and methodology for control logic, pipelines, and memory subsystems
• Define safety and liveness properties, model check for corner case behavior
• Guide designers in writing formal-friendly RTL and assertions
• Analyze convergence issues, coverage gaps, and create abstraction models
• Integrate formal sign-off into project milestones
Required Skills:
• 8+ years of formal verification experience with CPUs or processors
• Strong with JasperGold, VC Formal, OneSpin or equivalent
• Expertise in SVA/PSL, abstraction modeling, and formal coverage closure
• Strong computer architecture background (pipeline, MMU, interrupt logic)
• Excellent problem-solving, convergence debugging, and documentation skills
Interested,please drop your updated CV to janagaradha.n@acldigital.com
ACL Digital
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