4 Verification Engineering Jobs

About the Role: We are seeking a highly experienced Verification Engineer to join our dynamic team, driving innovation in advanced verification methodologies for complex semiconductor designs. You will play a key role in architecting, developing, and deploying verification methodologies for industry-leading IPs and sub-systems. Key Responsibilities: Lead the deployment of verification tools, platforms, and strategies for complex IPs Drive simulation-based and hardware-assisted verification efforts, including debugging and root cause analysis Apply expertise in a broad range of verification technologies, including simulation, static, and formal verification Develop and enhance verification methodologies, including verification cockpits and CAD flows Collaborate cross-functionally with IP design and DV teams as well as tools teams to ensure product quality Mentor and guide junior engineers, fostering a culture of technical excellence Qualifications: 10+ years of experience in verification engineering for complex hardware systems Deep expertise in simulation and debug, with a proven track record of silicon success Hands-on experience with Static/ Formal verification tools and methodologies Experience developing and deploying verification methodologies, including verification cockpits and CAD flows Exposure to hardware-assisted verification environments (FPGA prototyping, emulation) is a strong plus Strong analytical, problem-solving, and communication skills Bachelors or Masters in Electrical Engineering, Computer Engineering, or related field Familiarity with industry-standard verification languages (SystemVerilog, UVM, SVA) Experience with scripting and automation (Python, Perl, TCL) Track record of technical leadership and cross-functional collaboration Why Synopsys: Join a team that powers innovation and values agility, courage, excellence, and trust. We offer opportunities to work on cutting-edge technology and make a real impact. Show more Show less

As a Senior Verification Engineer for Optical Transport, you will play a crucial role in ensuring the quality and reliability of DWDM transmission systems. Your responsibilities will include designing and executing test cases, automating testing processes, and collaborating closely with architects and developers to enhance product performance. This is an excellent opportunity to deepen your expertise in optical networking and automation. You have: Graduate or Postgraduate in Engineering with a strong background in telecommunications, networking, or related fields. 7+ years of experience in testing and validation of optical networking technologies, including DWDM and OTN. Experience in designing and executing comprehensive test plans to validate new DWDM transmission system features. Ability to identify, analyze, and report software defects, collaborating with architects and developers for resolution. It would be nice if you also had: Experience in developing and implementing automated test scripts to enhance efficiency and test coverage. Experience in conducting regression testing across various network configurations to ensure system stability and performance. Familiarity with industry-standard tools and technologies related to optical transport networks. Design and execute comprehensive test plans to validate new DWDM transmission system features. Identify, analyze, and report software defects, collaborating with architects and developers for resolution. Develop and implement automated test scripts to enhance efficiency and coverage. Conduct regression testing with various network configurations to ensure system stability. Gain expertise in optical networking technologies, including DWDM and high-speed data transmission. Enhance debugging and troubleshooting skills by working with complex networking scenarios. Work closely with cross-functional teams to drive continuous quality improvements. Stay updated with the latest advancements in automation and optical transport systems.

The Role: The Subject Matter Expert - Verification & Validation will lead the development and execution of comprehensive V&V strategies across diverse platforms and product lines. The role requires deep expertise in V&V methodologies, tools, and standards compliance (e.g., ASPICE, ISO 26262), with a strong focus on enhancing quality, safety, and innovation in automotive system validation processes. Area of Responsibility Develop and lead V&V strategies for system-level and integration testing Manage and optimize V&V toolchains Design and implement automation frameworks Ensure process compliance with ASPICE, ISO 26262 Lead debugging and diagnostics of embedded systems Collaborate on MBSE and SysML for V&V planning Innovate V&V approaches for SDVs, EVs, and advanced electronics Dimension of Function: Lead cross-functional V&V initiatives impacting multiple engineering teams and product programs Ownership of V&V processes, toolchain configuration, and automation frameworks Ensure compliance with industry safety and quality standards Provide technical leadership and mentorship in V&V best practices Drive continuous improvement and innovation in validation methodologies Contacts: Global Head of SW Quality, Innovation and V&V Project Managers System Engineers Software & Hardware Development Teams OEM and Tier-1 Automotive Clients Tool Vendors (e.g., dSPACE, Vector, NI) Knowledge / Experience V&V methodologies (MIL, SIL, HIL, VIL, DIL) Programming: Python, CAPL, LabVIEW Tools: dSPACE, Vector, NI, IPG, Synopsys FPGA modeling and debugging MBSE and SysML Standards: ISO 26262, ISO 21434, ASPICE Certifications (Preferred): dSPACE, Vector, NI tool certifications ASPICE, ISO 26262 functional safety certifications MathWorks or related tool certifications

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in mixed signal IC verification / design experience Expertise in analog and mixed-signal circuit topologies Define verification plan based on product specifications and application use-cases Develop top-level AMS test benches using Cadence / System Verilog / UVM framework Simulate and validate verification plan use-cases Work with design team to debug and support issues Manage bug tracking Create automated regression flows Document and organize regression results Conduct AMS waveform review master the full AMS verification process. Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit