Design Verification Engineer ACL Digital

1.0 - 3.0 years

0 Lacs

hyderabad, telangana, india

On-site

Hi all, #ACL Digital is Hiring DV Engineers Experience: 1 - 3 years Strong expertise in UVM-based verification. Hands-on IP-level verification exposure Solid understanding of serial protocols are a must. Notice Period: 030 Days Location: Hyderabad Interested please share profiles at [HIDDEN TEXT] Thanks, K Himabindu

Posted 1 day ago

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Principal Digital Design Engineer Astera Labs

12.0 - 14.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com. We are seeking a Principal Digital Design Engineer with deep expertise in high-performance controller an...

Posted 1 week ago

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Senior Digital Design Engineer - SOC Astera Labs

5.0 - 7.0 years

0 Lacs

Bengaluru, Karnataka, India

On-site

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . We are seeking a Senior Digital Design Engineer w...

Posted 2 months ago

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Staff IP Design Verification CXL Synopsys

8.0 - 13.0 years

3 - 14 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced Engineers. Technical Expertise Needed: BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP/SoC. Knowledge of one or more of...

Posted 4 months ago

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